US 6,209,020 B1 · Distributed pipeline memory architecture for a computer system with even and odd pids

Abstract

A computer system architecture in which each processor has its own memory, strategically distributed along the stages of an execution pipeline of the processor, to provide fast access to often used information, such as the contents of the address and data registers, the program counter, etc. Memory storage is strategically located in close physical proximity to a stage in an execution pipeline at which memory is commonly or repeatedly accessed. Coupled to the pipeline at various stages are small memory cells for storing information that is consistently and repeatedly requested at that stage in the execution pipeline. The speed of the execution pipeline in a processor is critical to overall performance of the processor and the computer architecture of the present invention as a whole. To that end, the clock cycle time at which the pipeline is operated is increased as much as the operating characteristics of the logic and associated circuitry will allow. Generally, access times for memory are slower than the clock cycle times at which the pipeline logic can operate. Thus, there is a point of diminishing return at which increasing the clock cycle time of the pipeline is less advantageous if the pipeline must wait for memory access to complete. Thus, there is provided two sets of strategically located memory cells distributed along the execution pipeline of a processor, and alternately accesses the memory cells.

Claims18

Dependent claims

An execution pipeline having a plurality of stages concurrently executing a plurality of processes, the execution pipeline comprising:

a first memory cell located within a first stage and coupled to a first register;
a second memory cell located within the first stage and coupled to the first register;
a first selector located within the first stage and coupled to the first memory cell and the second memory cell, the first selector selecting one of the first memory cell and the second memory cell to provide data input to the first register;
a third memory cell located within a second stage and coupled to a second register;
a fourth memory cell located within the second stage and coupled to the second register;
and
a second selector located within the second stage and coupled to the third memory cell and the fourth memory cell, the second selector selecting one of the third memory cell and the fourth memory cell to provide data input to the second register.

4 more elements

An execution pipeline having a plurality of stages concurrently executing a plurality of processes, the execution pipeline comprising:

a plurality of registers coupled in communication;
a first memory cell located within a first stage and coupled to a first register, the first memory cell having stored therein data accessible by a first process being executed by the first stage;
a second memory cell located within the first stage and coupled to the first register, the second memory cell having stored therein data accessible by the first process;
a first selector located within the first stage and coupled to the first memory cell and the second memory cell, the first selector selecting one of the first memory cell and the second memory cell for access by the first process to provide data input to the first register;
a third memory cell located within a second stage and coupled to a second register, the third memory cell having stored therein data accessible by a second process being executed by the second stage;
a fourth memory cell located within the second stage and coupled to the second register, the fourth memory cell having stored therein data accessible by the second process;
and
a second selector located within the second stage and coupled to the third memory cell and the fourth memory cell, the second selector selecting one of the third memory cell and the fourth memory cell for access by the second process to provide data input to the second register.

5 more elements

Dependencies are inferred from the claim text.

Distributed pipeline memory architecture for a computer system with even and odd pids

Life of this patent

Distributed pipeline memory architecture for a computer system with even and odd pids

Life of this patent

Abstract

Claims18