Look-ahead LMS technique
AssigneeLucent Technologies Inc.
InventorMohit Kishore Prasad
Life of this patent
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Abstract
An apparatus and a technique for adapting a plurality of tap weights in an adaptive filter where tap weights are adapted utilizing every other sample of a sequence of samples. The apparatus comprises a sampler circuit for sampling an input signal producing a sequence of samples; a tap weight processor for generating the plurality of tap weights coupled to the sampler circuit; wherein the plurality of tap weights are adapted utilizing every other sample of the sequence of samples.
Claims25
A method of adapting tap weights in an adaptive filter, the method comprising the steps of:
- generating a first filter output and a second filter output utilizing a first plurality of tap weights;
- generating errors corresponding to said first filter output and said second filter output;
- updating a first order correlate using a pair of new samples and a previous correlate;
- generating an error using said errors corresponding to said first filter output and said second filter output and using said first order correlate;
- and
- generating a next plurality of tap weights.
A circuit for adapting tap weights of an adaptive filter in an integrated circuit comprising:
- a tap weight processor for generating a plurality of tap weights in response to a sequence of digital samples, said tap weight processor comprising means for generating an error;
- wherein said error is e(n+1) which is a function of e(n), e′(n+1) and φ1(n+1), where e is an error, e′ is an intermediate error, φ1 is a correlation coefficient, n is a time, and said plurality of tap weights are adapted at every second sample.
A circuit for adapting tap weights of an adaptive filter in an integrated circuit comprising:
- a tap weight processor for generating a plurality of tap weights in response to a sequence of digital samples, said tap weight processor further comprising means for updating a first order correlate using a pair of new samples and a previous correlate;
- wherein said first order correlate is φ1(n+1), said pair of new samples are x(n+1) and x(n), and said previous correlate is φ1(n−1).
An integrated circuit adaptive finite impulse response filter comprising:
- a plurality of multiplier circuits having an input and an output wherein each of said plurality of multiplier circuits multiplies a signal applied to said input by a predetermined tap weight providing a weighted signal which is applied to said output;
- a plurality of delay stages coupled in sequence such that each input of each of said plurality of multiplier circuits has one of said plurality of delay stages coupled between;
- a summer circuit coupled to each of the outputs of each of said plurality of multiplier circuits wherein said summer circuit provides an output signal which is a summation of said weighted signals;
- a tap weight processor coupled to each of said plurality of multiplier circuits for providing said predetermined tap weight, said tap weight processor comprising means for generating an error;
- wherein said error is e(n+1) which is a function of e(n), e′(n+1) and φ1(n+1), where e is an error, e′ is an intermediate error, φ1 is a correlation coefficient, n is a time, and tap weights are adapted utilizing every other sample of a sequence of samples.
An integrated circuit adaptive finite impulse response filter comprising:
- a plurality of multiplier circuits having an input and an output wherein each of said plurality of multiplier circuits multiplies a signal applied to said input by a predetermined tap weight providing a weighted signal which is applied to said output;
- a plurality of delay stages coupled in sequence such that each input of each of said plurality of multiplier circuits has one of said plurality of delay stages coupled between;
- a summer circuit coupled to each of the outputs of each of said plurality of multiplier circuits wherein said summer circuit provides an output signal which is a summation of said weighted signals;
- a tap weight processor coupled to each of said plurality of multiplier circuits for providing said predetermined tap weight, said tap weight processor further comprising means for updating a first order correlate using a pair of new samples and a previous correlate;
- wherein said first order correlate is φ1(n+1), said pair of new samples are x(n+1) and x(n), and said previous correlate is φ1(n−1).
Dependencies are inferred from the claim text.