Domino to static circuit technique

A method for converting a dynamic circuit to a static circuit, said method comprising:

• preparing a mask set, including transistor layout masks and transistor interconnection masks, said mask set being for use in fabricating said dynamic circuit including all required transistors and interconnections for said dynamic circuit in a first circuit configuration, said first circuit configuration including a clock terminal arranged for receiving a clock signal, said first circuit configuration being selectively operable to provide a predetermined logic function, said predetermined logic function being synchronized relative to said clock signal;
• and
• changing predetermined ones of said interconnections by modification of only said transistor interconnection masks, said dynamic circuit being thereby converted into a static circuit having a second circuit configuration, said second circuit configuration being disconnected from said clock terminal, said second circuit configuration being selectively operable to provide said predetermined logic function in a manner which is unsynchronized relative to said clock signal.

A method for converting a dynamic circuit to a static circuit, said method comprising:

• preparing a mask set, including transistor layout masks and transistor interconnection masks, said mask set being for use in fabricating said dynamic circuit including all required transistors and interconnections for said dynamic circuit;
• and
• changing predetermined ones of said interconnections by modification of only said transistor interconnection masks, said dynamic circuit being thereby converted into a static circuit, wherein said dynamic circuit comprises first transistor connected to a first logic level, a fourth transistor connected to a second logic level, and second and third transistors connected in series between said first and fourth transistors, respectively, said first and fourth transistors having a gate terminal of each of said first and fourth transistors arranged to receive a clock input signal, said second and third transistors having a gate terminal of each of said second and third transistors arranged to receive input signals.

A mask set for fabricating an integrated circuit, said mask set comprising:

• a number of transistor layout masks for fabricating transistor circuitry, said masks including a layout having transistors for a dynamic circuit having a first circuit configuration, said first circuit configuration including a clock terminal arranged for receiving a clock signal, said first circuit configuration being selectively operable to provide a predetermined logic function, said predetermined logic function being synchronized relative to said clock signal, said masks further including transistors for converting the dynamic circuit into a logically equivalent static circuit having a second circuit configuration, said second circuit configuration being disconnected from said clock terminal, said second circuit configuration being selectively operable to provide said predetermined logic function in a manner which is unsynchronized relative to said clock signal;
• and
• an interconnect layer mask for interconnecting the transistors, wherein the dynamic circuit of said first configuration is convertible into the static circuit of said second configuration by modification of solely the interconnect layer mask.