High frequency clock signal distribution utilizing CMOS negative impedance terminations

An integrated circuit comprising:

• a clock generator that outputs a clock signal that alternates between a high level and a low level;
• a clock inverter circuit that provides the complement of said clock signal;
• a transmission line having a first conductor and a second conductor, wherein said first conductor is coupled to said clock signal and said second conductor is coupled to said clock signal complement;
• and
• a plurality of terminations coupled to said first conductor and said second conductor, said plurality of terminations providing a negative impedance to said first conductor and said second conductor that boost transmission times of said clock signal and said clock signal complement such that operation of sub-circuits connected to said transmission line is synchronized.

A method for synchronizing circuit operation within an integrated circuit having a high frequency clock, said system comprising:

• providing a clock signal having a plurality of transitions that alternates between a high level and a low level;
• providing the complement of said clock signal utilizing a clock inverter circuit;
• coupling said clock signal to a first conductor of a transmission line and said clock signal complement to a second conductor of said transmission line;
• and
• connecting a plurality of terminations to said first conductor and said second conductor, said plurality of terminations providing a negative impedance to said first conductor and said second conductor that boost transmission times of said clock signal and said clock signal complement such that operation of sub-circuits connected to said transmission line is synchronized.