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US 6,208,685 B1Granted
Matched filter
AssigneeFujitsu Limited
InventorHiroshi Yamazaki
Life of this patent
Estimating the term…
Abstract
An average value calculating circuit comprises capacitors C1 to Cn with one end of each capacitor supplied with reference voltage VSS, switching elements SW11 to SW1n connected between inputs D1 to Dn and the other ends of capacitors C1 to Cn, respectively, common wiring COM, switching elements SW21 to SW2n connected between the other ends of capacitors C1 to Cn and common wiring COM and resetting switching element SWr with one end connected to common wiring COM and the other end supplied with reference voltage VTT. When one of a group consisting of switching elements SW11 to SW1n and SWr and another group consisting of switching elements SW21 to SW2n is on, the others are off, substantially.
Claims14
A matched filter comprising:
- a shift register having a plurality of cascaded delay elements, a first stage of said delay elements receiving a spread spectrum signal, said delay elements being clocked by a clock signal to provide a parallel signal from outputs thereof;
- a coincidence degree calculating circuit for calculating degrees of coincidence between said parallel signal and a pseudorandom noise;
- a plurality of capacitors each having one end supplied with a first reference potential;
- a plurality of first switching elements each connected between said output of corresponding one of said delay elements and other end of corresponding one of said capacitors;
- a common conductor;
- a plurality of second switching elements connected between said other end of corresponding one of said capacitors and said common conductor;
- and
- a resetting switching element with its one end connected to said common conductor and its other end supplied with a second reference potential;
- wherein said capacitors comprises:
- a plurality of first capacitor elements each with its one end supplied with said first reference potential, other end thereof being said other end of corresponding one of said capacitors;
- a plurality of second capacitor elements each with its one end supplied with a third reference potential;
- and
- a plurality of third switching elements each connected between said other end of corresponding one of said first capacitor elements and its other end of corresponding one of said second capacitor elements,
- wherein when one of a first group consisting of said first switching elements and said resetting switching element, and a second group consisting of said second switching elements is on, the other thereof is off, substantially, and
- wherein said third switching elements are controlled by weight data.
12 more elements
A communication device including a matched filter, said matched filter comprising:
- a shift register having a plurality of cascaded delay elements, a first stage of said delay elements receiving a spread spectrum signal, said delay elements being clocked by a clock signal to provide a parallel signal from outputs thereof;
- a coincidence degree calculating circuit for calculating degrees of coincidence between said parallel signal and a pseudorandom noise;
- a plurality of capacitors each having one end supplied with a first reference potential;
- a plurality of first switching elements each connected between an output of corresponding one of said delay elements and other end of corresponding one of said capacitors;
- a common conductor;
- a plurality of second switching elements each connected between said other end of corresponding one of said capacitors and said common conductor;
- and
- a resetting switching element with its one end connected to said common conductor and its other end supplied with a second reference potential;
- wherein said capacitors comprises:
- a plurality of first capacitor elements each with its one end supplied with said first reference potential, other end thereof being said other end of corresponding one of said capacitors;
- a plurality of second capacitor elements each with its one end supplied with a third reference potential;
- and
- a plurality of third switching elements each connected between said other end of corresponding one of said first capacitor elements and its other end of corresponding one of said second capacitor elements,
- wherein when one of a first group consisting of said first switching elements and said resetting switching element, and a second group consisting of said second switching elements is on, the other thereof is off, substantially, and
- wherein said third switching elements are controlled by weight data.
12 more elements
An average value calculating circuit, comprising:
- a plurality of capacitors having a first end and a second end, each second end being supplied with a first reference potential;
- and
- a switching circuit sampling and holding charges corresponding to input signals to said capacitors and connecting said capacitors in parallel while isolating the input signals to output an average value corresponding to an average voltage of said capacitors, said switching circuit comprising:
- a plurality of first switching elements, a first end of each first switching element connected to an input for receiving the input signals and a second end connected to a corresponding first end of one of said capacitors,
- a common conductor,
- a plurality of second switching elements, a first end of each second switching element connected to the first end of each corresponding capacitor and a second end connected to said common conductor, and
- a resetting switching element having a first end connected to said common conductor and a second end supplied with a second reference potential,
- wherein said first switching elements and said resetting switching element comprise a first group, and said second switching elements comprise a second group, and when one of the first and second groups is on, the other thereof is off.
5 more elements
A correlation value calculating circuit, comprising:
- a coincidence degree calculating circuit calculating a coincidence degree between each of a plurality of input signals and corresponding digits of a pseudorandom noise, and having outputs providing each of the coincidence degrees;
- a plurality of capacitors having a first end and a second end, each second supplied with a first reference potential;
- and
- a switching circuit, comprising:
- a plurality of first switching elements, a first end of each first switching element connected to a corresponding one of the outputs of the coincidence degrees, and a second end of each first switching element connected to a corresponding first end of one of said capacitors,
- a common conductor,
- a plurality of second switching elements, a first end of each second switching element connected to the first end of each corresponding capacitor and a second end connected to said common conductor, and
- a resetting switching element having a first end connected to said common conductor and a second end supplied with a second reference potential,
- wherein said first switching elements and said resetting switching element comprise a first group, and said second switching elements comprise a second group, and when one of the first and second groups is on, the other thereof is off.
6 more elements
A matched filter comprising:
- a shift register having a plurality of cascaded delay elements, a first one of said delay elements receiving a spread spectrum signal, the delay elements being clocked by a clock signal to provide delayed signals from outputs thereof;
- a coincidence degree calculating circuit calculating a coincidence degree between each of the delayed signals and corresponding digits of a pseudorandom noise, and having outputs providing each of the coincidence degrees;
- a plurality of capacitors, each having a first end and a second end, each second end supplied with a first reference potential;
- and
- a switching circuit, comprising:
- a plurality of first switching elements, a first end of each first switching element connected to a corresponding one of the outputs of the coincidence degrees, and a second end of each first switching element connected to a corresponding first end of one of said capacitors,
- a common conductor,
- a plurality of second switching elements, a first end of each second switching element connected to the first end of each corresponding capacitor and a second end connected to said common conductor, and
- a resetting switching element having a first end connected to said common conductor and a second end supplied with a second reference potential,
- wherein said first switching elements and said resetting switching element comprise a first group, and said second switching elements comprise a second group, and when one of the first and second groups is on, the other thereof is off.
7 more elements
A multi-bit matched filter receiving a multi-bit stream of a spread spectrum signal into a plurality of corresponding matched filters, each of said matched filters comprising:
- a shift register having a plurality of cascaded delay elements, a first one of said delay elements receiving a spread spectrum signal, the delay elements being clocked by a clock signal to provide delayed signals from outputs thereof;
- a coincidence degree calculating circuit calculating a coincidence degree between each of said delayed signals and corresponding digits of a pseudorandom noise, and having outputs providing each of the coincidence degrees;
- a plurality of capacitors, each having a first end and a second end, each second end supplied with a first reference potential;
- and
- a switching circuit, comprising:
- a plurality of first switching elements, a first end of each first switching element connected to a corresponding one of the outputs of the coincidence degrees, and a second end of each first switching element connected to a corresponding first end of one of said capacitors,
- a common conductor,
- a plurality of second switching elements, a first end of each second switching element connected to the first end of each corresponding capacitor and a second end connected to said common conductor, and
- a resetting switching element having a first end connected to said common conductor and a second end supplied with a second reference potential,
- wherein said first switching elements and said resetting switching element comprise a first group, and said second switching elements comprise a second group, and when one of the first and second groups is on, the other thereof is off.
7 more elements
A communication device having a matched filter, said matched filter comprising:
- a shift register having a plurality of cascaded delay elements, a first one of said delay elements receiving a spread spectrum signal, the delay elements being clocked by a clock signal to provide delayed signals from outputs thereof;
- a coincidence degree calculating circuit calculating a coincidence degree between each of said delayed signals and corresponding digits of a pseudorandom noise, and having outputs providing each of the coincidence degrees;
- a plurality of capacitors, each having a first end and a second end, each second end supplied with a first reference potential;
- and
- a switching circuit, comprising:
- a plurality of first switching elements, a first end of each first switching element connected to a corresponding one of the outputs of the coincidence degrees, and a second end of each first switching element connected to a corresponding first end of one of said capacitors,
- a common conductor,
- a plurality of second switching elements, a first end of each second switching element connected to the first end of each corresponding capacitor and a second end connected to said common conductor, and
- a resetting switching element having a first end connected to said common conductor and a second end supplied with a second reference potential,
- wherein said first switching elements and said resetting switching element comprise a first group, and said second switching elements comprise a second group, and when one of the first and second groups is on, the other thereof is off.
7 more elements
A matched filter, comprising:
- a plurality of first capacitor elements, each having a first end and a second end, the second end supplied with a first reference potential;
- a plurality of first switching elements, a first end of each first switching element connected to a corresponding one of a plurality of delay elements, and a second end of each first switching element connected to a corresponding first end of one of said first capacitor elements;
- a resetting switching element having a first end connected to a common conductor and a second end supplied with a second reference potential;
- a plurality of second capacitor elements, each having a first end and a second end, the second end supplied with a third reference potential;
- a plurality of second switching elements, each having a first end and a second end, the first end of each second switching element connected to the first end of a corresponding one of said first capacitor elements, and the second end of each second switching element connected to the common conductor;
- and
- a plurality of third switching elements, each having a first end and a second end, the first end of each third switching element connected to the first end of a corresponding one of said first capacitor elements, and the second end of each third switching element connected to the first end of a corresponding one of said second capacitor elements.
4 more elements
Dependencies are inferred from the claim text.