Circuit for performing high-speed, low latency frame relay switching with support for fragmentation and reassembly and channel multiplexing

An ASIC for switching frame-relay signals, the ASIC comprising:

• a receiving means for receiving HDLC signals, each HDLC signal having a header;
• an input processing means for real-time concurrent multiple processing of the HDLC signals;
• a storing means for storing the HDLC signals processed by said input processing means;
• an output processing means for real-time concurrent multiple processing of the stored HDLC signals;
• a transmitting means for transmitting the HDLC signals;
• and
• an interfacing means for interfacing said receiving means, said input processing means, said storing means, said output processing means, and said transmitting means to a CPU.

A circuit for switching frame-relay signals, said circuit comprising:

• a first processing block comprising a receiving means for receiving HDLC signals having a header and a first processing means for real-time concurrent multiple processing of the HDLC signals;
• a memory management block for managing the storage of the HDLC signals processed by said first processing means;
• a second processing block comprising a second processing means for real-time concurrent multiple processing of the stored HDLC signals and a transmitting means for transmitting the stored HDLC signals after processing by said second processing means;
• and
• an interface block for interfacing said first processing block, said memory management block, and said second processing block to a CPU.

A method for switching frame-relay signals, comprising the steps of:

• receiving, in an ASIC, HDLC signals, the HDLC signals having a header;
• performing real-time concurrent multiple input processing on the HDLC signals in said ASIC;
• storing the input processed HDLC signals;
• performing real-time concurrent multiple output processing on the stored HDLC signals in said ASIC;
• and
• transmitting the output processed HDLC signals from said ASIC.

A circuit for switching frame-relay signals, said circuit comprising:

• a receiver configured to receive HDLC signals, each HDLC signal having a header;
• an input processor configured to process real-time concurrent multiple HDLC signals;
• a storage unit configured to store the HDLC signals processed by said input processing means;
• an output processor configured to process real-time concurrent multiple HDLC signals;
• a transmitter configured to transmit the HDLC signals;
• and
• an interface configured to interface the receiver, the input processor, the buffer, the output processor, and the transmitter to a CPU.

An ASIC configured to switch frame-relay signals, comprising:

• a receiver configured to receive HDLC signals, each HDLC signal having a header;
• an input processor configured to process real-time concurrent multiple HDLC signals;
• a storage unit configured to store the HDLC signals processed by said input processing means;
• an output processor configured to process real-time concurrent multiple HDLC signals;
• a transmitter configured to transmit the HDLC signals;
• and
• an interface configured to interface the receiver, the input processor, the buffer, the output processor, and the transmitter to a CPU.

A method for switching frame-relay signals, comprising the steps of:

• receiving HDLC signals, each signal having a header;
• performing real-time concurrent multiple input processing on the HDLC signals;
• storing the input processed HDLC signals;
• performing real-time concurrent multiple output processing on the stored HDLC signals;
• and
• transmitting the output processed HDLC signals.