Synchronous semiconductor memory having an improved reading margin and an improved timing control in a test mode

A synchronous semiconductor memory comprising:

• a memory control means, receiving a pre-CAS signal and a test-CAS signal and being responsive to a mode discrimination signal, for outputting said test-CAS signal as a CAS signal when said mode discrimination signal is active to indicate a test mode, and said pre-CAS signal as said CAS signal when said mode discrimination signal is inactive;
• a data amplifier control means receiving said CAS signal and a clock signal and for generating a data amplifier enable signal at a delay in time with said clock signal when said mode discrimination signal is inactive, said data amplifier control means generating said data amplifier enable signal by delaying said CAS signal independently of said clock signal when said mode discrimination signal is inactive;
• and
• a memory cell array responding to a column selection signal to output data stored in said memory cell array to associated data amplifiers, so that when said associated data amplifiers are enabled by said data amplifier enable signal, said data is amplified and outputted by said associated data amplifiers.