Semiconductor storage device including column pre-decoder circuit for preventing multiple selection of bit lines

A semiconductor storage device comprising:

• a memory cell array on which a plurality of memory cells are arranged in a matrix form using word lines and bit lines respectively corresponding to rows and columns, which are designated based on address signals being given from an external;
• a row address buffer circuit for inputting the address signals in synchronization with an external clock signal to provide a row address signal;
• a row decoder circuit for decoding the row address signal to selectively activate a corresponding word line;
• a column address buffer circuit for inputting the address signals in synchronization with the external clock signal to provide a column address signal;
• a column address counter circuit for converting the column address signal to internal signals, which designate continuing column addresses of a prescribed burst length;
• a column pre-decoder circuit for pre-decoding the internal signals in response to a pulse signal so as to produce column address pre-decode signals;
• a column decoder circuit for decoding the column address pre-decode signals to produce column selecting signals;
• a sense amplifier circuit consisting of a plurality of sense amplifiers, each of which is coupled with a pair of adjoining bit lines;
• and
• a plurality of column selecting transistors, each pair of which are respectively coupled between each pair of the adjoining bit lines and data lines by way of each sense amplifier and each pair of which are simultaneously controlled in conduction in response to each of the column selecting signals,
• wherein data are to be read from or written to the memory cells by way of the data lines, and said transistors are in a non-conductive state when inputting said addresses and balancing said data lines.