US 6,208,575 B1 · Dynamic memory array bit line sense amplifier enabled to drive toward, but stopped before substantially reaching, a source of voltage

Abstract

A high performance dynamic memory array architecture is disclosed in several embodiments, along with various embodiments of associated supporting circuitry. An exemplary 18 MBit memory array includes four banks of arrays. Within each memory bank, a row of bit line sense amplifiers is implemented in the holes between each pair of array blocks. After a selected word line is driven active, and a signal from each associated memory cell is developed on the corresponding bit line pair, both PMOS and NMOS sensing of the associated bit line sense amplifiers are simultaneously enabled. The PMOS sense amplifier drives the bit line having a higher voltage toward VDD, but this PMOS sensing is terminated before the high-going bit line substantially reaches the full VDD voltage, thus allowing the bit line to quickly be driven to a high level with a reduced “exponential tail.” NMOS sensing continues while the word line and array select lines are left high, so that charge sharing between the sense amplifier nodes, the bit lines, and the memory cell storage node itself contribute to determining the final restore level that is “written” back into the selected memory cell. The PMOS sense timing may be accomplished to ensure a written high level that is substantially independent of VDD and substantially independent of process and temperature variations. The selected word line is then brought low, the NMOS sensing terminated, and the array block precharged.

Claims87

Dependent claims

In an integrated circuit including a first cross-coupled transistor pair for sensing and amplifying a differential voltage between first and second circuit nodes, a method of sensing the differential voltage and driving to a first voltage whichever first or second circuit node is closer in voltage to the first voltage, said method comprising:

driving the first cross-coupled transistor pair toward a second voltage beyond the first voltage, thereby driving toward the second voltage whichever first or second circuit node is closer in voltage to the first voltage;
then
stopping the driving of the first cross-coupled transistor pair at a time before the driven circuit node substantially reaches the second voltage such that the driven node is decoupled from any source of the second voltage, remains decoupled from any other source of voltage, and reaches a final voltage substantially equal to the first voltage.

In an integrated circuit including a dynamic memory array having a bit line sense amplifier circuit for sensing a differential voltage between a true bit line and a complement bit line and restoring a high voltage level on the true or complement bit line having a higher initial voltage and likewise into a selected memory cell if coupled thereto, and restoring a low voltage level on the other of the true or complement bit line and likewise into a selected memory cell if coupled thereto, a method of operating the integrated circuit comprising:

providing a cross-coupled PMOS transistor pair within the bit line sense amplifier circuit and coupled to the true and complement bit lines, said cross-coupled PMOS transistor pair having a common-source terminal;
coupling the common-source terminal of the cross-coupled PMOS transistor pair to a first power supply voltage that is greater than the initial bit line voltages, thereby driving the true or complement bit line having a higher initial voltage upward toward the first power supply voltage;
and
after a predetermined PMOS sense duration before the true or complement bit line driven high substantially reaches the first power supply voltage, decoupling the cross-coupled PMOS transistor pair from the first power supply voltage and from any other source of voltage, thereby achieving a restore high voltage level on the driven-high true or complement bit line that is substantially lower than the first power supply voltage.

1 more element

An integrated circuit comprising:

a dynamic memory an-ay having a bit line sense amplifier circuit for sensing a differential voltage between a true bit line and a complement bit line and restoring a high voltage level on the true or complement bit line having a higher initial voltage and likewise into a selected memory cell if coupled thereto, and for restoring a low voltage level on the other of the true or complement bit line and likewise into a selected memory cell if coupled thereto;
a cross-coupled PMOS transistor pair within the bit line sense amplifier circuit and coupled to the true and complement bit lines, said cross-coupled PMOS transistor pair having a common-source terminal;
first means for coupling the common-source terminal of the cross-coupled PMOS transistor pair to a first power supply voltage that is greater than the initial bit line voltages, thereby driving the true or complement bit line having a higher initial voltage upward toward the first power supply voltage, and for decoupling the cross-coupled PMOS transistor pair from the first power supply voltage and from any other source of voltage, after a predetermined PMOS sense duration before the true or complement bit line driven high substantially reaches the first power supply voltage, thereby achieving a restore high voltage level on the driven-high true or complement bit line that is substantially lower than the first power supply voltage.

An integrated circuit comprising:

a first dynamic memory array block including a first plurality of true and complement bit line pairs;
a first plurality of bit line sense amplifiers, each coupled to a respective one of the first plurality of complementary bit line pairs and each responsive to first and second sense amplifier enable signals, for sensing, when at least one of the first and second sense amplifier enable signals is driven active, a differential voltage between a respective true bit line and a respective complement bit line coupled thereto and for driving, for as long as the first sense amplifier enable signal remains active, the respective true or complement bit line having a higher initial voltage toward a first voltage to establish a restore high voltage level thereon, and for driving, for as long as the second sense amplifier enable signal remains active, the other of the respective true or complement bit lines toward a second voltage to establish a restore low voltage level thereon;
and
a sense amplifier timing circuit arranged to control the first and second sense amplifier enable signals such that the first sense amplifier enable signal, after being driven active, is driven inactive substantially before the respective true or complement bit line having a higher initial voltage substantially reaches the first voltage, thereby establishing a restore high voltage level that is substantially lower than the first voltage.

1 more element

Dependencies are inferred from the claim text.

Dynamic memory array bit line sense amplifier enabled to drive toward, but stopped before substantially reaching, a source of voltage

Life of this patent

Dynamic memory array bit line sense amplifier enabled to drive toward, but stopped before substantially reaching, a source of voltage

Life of this patent

Abstract

Claims87