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AssigneesUnited Memories, Inc., Nippon Steel Semiconductor Corporation
InventorKim C. Hardee
Estimating the term…
A sense amplifier for a very high density integrated circuit memory using CMOS technology is described. Each sense amplifier includes first and second local sense amplifier drive transistors, one connecting the P channel transistors to VCC; the other connecting the N channel transistors to VSS. A read amplifier circuit is provided within each sense amplifier and is operated by read control signals. Internal nodes of the latch of the sense amplifier are coupled by pass transistors that are responsive to column write control signals. Local data write driver transistors are also provided to selectively couple the pass transistors to VCC-Vt or VSS in response to further data write control signals. A relatively wider power line is coupled to the drive transistors to provide VCC thereto, and a narrower line is used to control those first sense amplifier drive transistors. Corresponding wide and narrow lines are used for the second local sense amplifier drive transistors which couple the N channel transistors to ground. Each sense amplifier may be shared between first and second pairs of bit lines through the use of isolation transistors and a corresponding isolation signal.
In an integrated circuit memory having a plurality of bit line pairs, a combination comprising a plurality of sense amplifiers;
A sense amplifier arrangement for an integrated circuit memory comprising, for each of a plurality of sense amplifiers:
A sense amplifier arrangement for an integrated circuit memory comprising, for each of a plurality of sense amplifiers:
Dependencies are inferred from the claim text.