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US 6,208,573 B1Granted
Semiconductor memory device
AssigneeKabushiki Kaisha Toshiba
InventorsTomoharu Tanaka, Hiroshi Nakamura, Toru Tanzawa
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device comprises memory cells, a bitline connected to the memory cells, a read circuit including a precharge circuit, and a first transistor connected between the bitline and the read circuit, wherein a first voltage is applied to a gate of the first transistor when the precharge circuit precharges the bitline, and a second voltage which is different from the first voltage is applied to the gate of the first transistor when the read circuit senses a change in a voltage of the bitline.
Claims7
A semiconductor memory device comprising:
- plural memory cells;
- a bitline connected to said memory cells;
- a capacitor element connected to said bitline via a transfer transistor;
- and
- a sense circuit for sensing an electric charge amount stored in said capacitor element, wherein said bitline is precharged via said transfer transistor responsive to a first voltage being applied to a gate of said transfer transistor, and a change in a voltage of said bitline is transferred to said capacitor element as a change in the electric charge amount stored in said capacitor element responsive to a second voltage, which is different from the first voltage, being applied to the gate of said transfer transistor.
2 more elements
A semiconductor memory device comprising:
- plural memory cells;
- a bitline connected to said memory cells;
- a capacitor element having a first electrode and second electrode, said first electrode being connected to said bitline via a transfer transistor having a MOS structure;
- a precharge circuit connected to said first electrode for applying a first voltage to said first electrode in a precharge operation;
- a sense circuit connected to said first electrode for sensing an electric charge amount stored in said capacitor element in a sense operation;
- and
- a controller for applying a second voltage to a gate of said transfer transistor during the precharge operation and for applying a third voltage, which is different from the second voltage, to the gate of said transfer transistor during the sense operation.
4 more elements
Dependencies are inferred from the claim text.