Semiconductor memory device having resistive bitline contact testing
AssigneeInternational Business Machines Corporation
InventorsR. Dean Adams, Robert E. Busch, Harold Pilo, George E. Rudgers
Life of this patent
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Abstract
A semiconductor memory device having resistive bitline contact testing includes memory cells, and wordline logic devices for concurrently activating two adjacent memory cells. The two adjacent memory cells are activated concurrently to allow higher current through a bitline contact for improved detection of resistive bitline contacts. A test cell may also be included to test the integrity of the bitline contact.
Claims20
A memory device comprising:
- a first and second memory cell;
- a bitline for transferring a data value to or from said first and second memory cell;
- a bitline contact coupling said bitline to said first and second memory cell;
- a first and second wordline signal for activating said first and second memory cell, respectively, to transfer said data value to said bitline;
- and
- a wordline logic device, receiving said first and second wordline signal and transmitting said first and second wordline signal to said first and second memory cell, respectively,
- wherein during a test of said bitline contact, said wordline logic device transmits said first and second wordline signal to said first and second memory cell essentially simultaneously.
A method for testing the resistance of a bitline contact in a memory device having memory cells comprising the steps of:
- a) writing a data value into adjacent memory cells sharing said bitline contact;
- b) reading said data value from said adjacent memory cells essentially simultaneously;
- and
- c) comparing said read data value of said adjacent memory cells with said written data value.
A SRAM memory array system comprising:
- a plurality of adjacent memory cells;
- a bitline pair for transferring data values to or from said plurality of adjacent memory cells;
- a plurality of bitline contacts coupling said bitline pair to said plurality of adjacent memory cells, each of said plurality of bitline contacts being shared between each of said plurality of adjacent memory cells, respectively;
- a plurality of wordline signals for activating said plurality of adjacent memory cells, for transferring said data values to said bitline pair;
- and
- a plurality of wordline logic devices, receiving said plurality of wordline signals, each of said plurality of wordline logic devices receiving two of said plurality of wordline signals, and transmitting said plurality of wordline signals to said plurality of adjacent memory cells,
- wherein during a test of each of said plurality of bitline contacts, each of said plurality of wordline logic devices transmits said two of said plurality of wordline signals to each of said plurality of adjacent memory cells essentially simultaneously.
Dependencies are inferred from the claim text.