Loading patent…
AssigneeFujitsu Limited
InventorsMitsutaka Ikeda, Tsutomu Taniguchi, Yoshikazu Homma
Estimating the term…
A semiconductor memory device comprises a detecting unit and a testing unit. The detecting unit detects a plurality of times a state of a predetermined terminal when the power is switched on, and activates the testing unit when all results of the detections show expected values. The device shifts to a connection testing mode by activation of the testing unit, and performs predetermined testing. Therefore, the testing can be performed by causing the device to shift to the testing mode without using terminals dedicated to testing. Besides, a shift to the connection testing mode by activation due to an erroneous operation or power-supply noise is prevented from occurring. In another semiconductor memory device the conversion circuit receives parallel testing patterns via a plurality of input terminals and converts the patterns into serial output patterns. Since the parallel testing patterns are converted into serial output patterns, connection testing can be performed even when the number of output terminals is small. Furthermore, another semiconductor memory device comprises an operation circuit and a conversion circuit. The operation circuit receives parallel testing patterns via a plurality of input terminals, performs a logic operation, and outputs parallel operation result patterns. The conversion circuit receives the parallel operation result patterns and converts the patterns into serial output patterns. The converted output patterns are sequentially output from output terminals. The testing patterns fed to the conversion circuit by the operation circuit can be reduced. Accordingly, the output patterns become shorter, and testing time is reduced.
A semiconductor memory device comprising a detecting unit for detecting a state of the predetermined terminal a plurality of times when the power is switched on and a testing unit which is activated when all results of the detections by said detecting unit show expected values.
A semiconductor memory device comprising:
A semiconductor memory device comprising:
A circuit board mounted with a semiconductor memory device, wherein the semiconductor memory device comprises:
A circuit board mounted with a semiconductor memory device, wherein the semiconductor memory device comprises:
A circuit board mounted with a semiconductor memory device, wherein the semiconductor memory device comprises:
A circuit board mounted with a semiconductor memory device, wherein the semiconductor memory device comprises:
A method for testing interconnection between a semiconductor memory device with a circuit board, wherein the semiconductor memory device comprises:
In a method for testing interconnection between a semiconductor memory device with a circuit board according to the present invention, wherein the semiconductor memory device comprises:
Dependencies are inferred from the claim text.