Redundancy test method for a semiconductor memory

A semiconductor memory device, comprising:

• an array of memory cells arranged in rows and columns, the array of memory cells having a normal section and a redundant section;
• a redundant test control that generates a redundant test activation signal, the redundant test activation signal having a test activation logic level and a test non-activation logic level;
• a normal decoder for selecting the normal section of the array of memory cells;
• a redundant decoder section for selecting the redundant section of the array of memory cells, the redundant decoder section comprising:
• programmable address selectors for receiving address bits and coupled to a power up node;
• a redundancy enable circuit coupled to the power up node;
• a decode gate having inputs coupled to the programmable address selectors and to the redundancy enable circuit;
• and
• a test decode having inputs coupled to the decode gate, coupled to a low order of the address bits, and coupled to the redundant test activation signal;
• a test address circuit that receives a test address, the test address selecting between the normal section and the redundant section when the redundant test activation signal is at the test activation logic level.