Method of and apparatus for sharing redundancy circuits between memory arrays within a semiconductor memory device

A redundancy memory configuration for a semiconductor memory device comprising:

• a. a plurality of main memory arrays each including a plurality of memory cells arranged in a matrix of main rows and main columns;
• b. a shared redundancy circuit coupled to the main memory arrays, including a plurality of redundancy rows;
• and
• c. a means for programming the shared redundancy circuit coupled between the main memory arrays and to the shared redundancy circuit for substituting one of the redundancy rows in the shared redundancy circuit for a main row having a defective memory cell.

A memory circuit comprising:

• a. a first main memory array including a first plurality of memory cells arranged into a first matrix of rows and columns;
• b. a first dedicated redundancy memory array coupled to the first main memory array and including a second plurality of memory cells arranged into first groups of redundant memory cells, wherein the first groups of redundant memory cells are substituted for memory cells within the first main memory array;
• c. a second main memory array including a third plurality of memory cells arranged into a second matrix of rows and columns;
• d. a second dedicated redundancy memory array coupled to the second main memory array and including a fourth plurality of memory cells arranged into second groups of redundant memory cells;
• and
• e. a shared redundancy memory array coupled to both the first and second main memory arrays and including a fifth plurality of memory cells arranged into third groups of redundant memory cells which are substituted for memory cells within both the first and second main memory arrays.