Multi-ported register structure utilizing a pulse write mechanism

Abstract

A system and method are disclosed which provide a pulse write mechanism to enable a port to write to a register structure without requiring a large amount of circuitry. One or more ports may be coupled to a register structure in a manner that enables the ports to write data to the register structure without requiring a large amount of circuitry. The ports may be coupled to the register structure in a manner that enables them the capability of reading data from the register structure without requiring additional circuitry beyond that required for a write operation. A preferred embodiment implements a single-ended write structure, wherein a data carrier (e.g., BIT line) is utilized to carry a data value desired to be written for a port. A preferred embodiment comprises a write pulse mechanism, such as a NFET, capable of setting the memory cell to an initial value before performing a write thereto. Before performing a write operation to a memory cell, the write pulse signal is fired causing the write pulse mechanism to initialize the memory cell to a high voltage value. If the value of the BIT line is the same as the value to which the memory cell was initialized, the memory access mechanism enables the memory cell to remain at such value. However, if the value of the BIT line is different than the initial value of the memory cell, the memory access mechanism transitions the memory cell to the value of the BIT line.

Dependencies are inferred from the claim text.