High voltage comparator

#This invention relates generally to semiconductor devices, and more particularly to a high voltage comparator for semiconductor devices, especially non-volatile semiconductor memory devices such as flash memory devices.

#Generally, a flash memory device comprises an address sequencer, row and column decoders, sense amplifiers, write amplifiers, and a memory cell array. An example of a flash memory device is described in U.S. Pat. No. 5,490,107, the disclosure of which is herein incorporated by reference. The memory cell array contains a plurality of memory cells arranged in rows and columns. Each memory cell is capable of holding a single bit of information. A column of memory cells in the memory cell array is commonly coupled to a bit line. The column decoder along with the address sequencer selects a bit line. Similarly, the memory cells arranged in a row of the memory cell array are commonly coupled to a word line. The row decoder and address sequencer selects a word line. Together the row and column decoders and the address sequencer selects an individual memory cell or a group of memory cells.

#The memory cells in the memory cell array of a flash memory device are generally grouped into sub-arrays called memory cell blocks. Each memory cell block is coupled to a sense amplifier and a write amplifier. The write amplifier (W/A) applies a set of predetermined voltages to store information in the selected memory cells. This action is referred to as a program or write operation. Similarly, a set of predetermined voltages applied to the selected memory cells allows information to be discriminated and retrieved by the sense amplifier (S/A). This action is referred to as a read operation.

#FIG. 1 is an top level block diagram of a flash memory device of the present invention;

#FIG. 2 is a top level block diagram of one embodiment of a clock control circuit;

#FIG. 3 is a block diagram of one embodiment of the shift register assembly of the clock control circuit of FIG. 2;

#I. Overview

#In FIG. 1, one embodiment of a synchronous flash memory is shown. The synchronous flash memory has a clock control circuit 2. The clock control circuit 2 receives an external clock signal 3, and combines the external clock signal with a trigger signal 5 to generate an internal clock signal 7. An address sequencer 4 receives the internal clock signal 7 and sequences through addresses and generates address signals synchronously to the internal clock signal 7. The address signals are provided to column and row buffers 6 and 8. The address signals are selectively modified and supplied to column and row decoder circuits 24 and 26. The column and row decoder circuits generate column and row decoded signals to select specific memory cells in the memory cell array 51 for read and program operations.

#Each memory cell has a construction similar to a MOS transistor, and as such, a memory cell has a source region and a drain region on a substrate. Between the substrate, the memory cell has a floating gate and a control gate. Information is stored in the memory cell, i.e. in the floating gate, by applying a set of predetermined voltages to the memory cell. Likewise, a set of predetermined voltages applied to the memory cell is used to read information contained in the memory cell.