Semiconductor memory device which continuously performs read/write operations with short access time

A semiconductor memory device in which a word line is selected based on a row address, and a bit line is selected based on a column address, and in which, in each write or read cycle, a plurality of data bits are written to or read from memory cells corresponding to a selected word line as a burst, said semiconductor memory device comprising:

• a plurality of write/read circuits for reading data from selected memory cells to said lines and writing data from said data lines to said memory cells;
• a column selector for distributing data from an input/output line to said data lines, and outputting data from said data lines to said input/output line;
• a plurality of data latches inserted into data line circuit portions between said column selector and said write/read circuits, for temporarily storing data to be written to or read from said memory cells as a burst;
• and
• a word line drive signal generating circuit which supplies a word line drive signal to said word line, and in which, in a write cycle, said word line drive signal is deactivated after a predetermined delay time corresponding to a time period required for finishing write operation of data stored in said latches from activation of a write/read operation start signal, and said word line drive signal is activated after a predetermined delay time required for the precharge of said bit lines from the time said word line signal is deactivated, and, in a read cycle, after a predetermined delay time from activation of a word line in response to the activation of a write/read operation start signal, said word line drive signal is deactivated and a precharge operation of said bit lines is performed.

A semiconductor memory device in which a word line is selected based on a row address, and a bit line is selected based on a column address, and in which, in each write or read cycle, a plurality of data bits are written to or read from memory cells corresponding to a selected word line as a burst, said semiconductor memory device comprising:

• a plurality of write/read circuits for reading data from said memory cells to said data lines and writing data from said data lines to said memory cells;
• a column selector for distributing data from an input/output line to said data lines, and outputting data from said data lines to said input/output line;
• a plurality of data latches inserted between said column selector and said write/read circuits, for temporarily storing data to be written to or read from said memory cells as a burst;
• and
• a word line drive signal generating circuit which, when write cycles or read cycles continue, after a word line drive signal is deactivated in response to the generation of a write end signal or read end signal, said word line drive signal is activated after a predetermined delay time corresponding to a time period required for the precharge of bit lines, and, in the first write or read cycle, said word line drive signal is activated immediately after the generation of said write/read operation start signal.