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US 6,208,562 B1Granted
Digital memory and method of operation for a digital memory
AssigneeInfineon Technologies AG
InventorsMartin Zibert, Bret Johnson
Life of this patent
Estimating the term…
Abstract
The digital memory has at least one data line and address lines. It also has a switching unit that, in an active state, inverts signals on the data line or on at least one of the address lines and that, in an inactive state, leaves the signals unchanged. In a first operating mode, the switching unit is in the same state for writing and reading. In a second operating mode, the switching unit is in respectively opposite states for writing and for reading.
Claims4
A memory configuration, comprising:
- a digital memory that includes:
- memory cells;
- at least one data line for writing data to said memory cells and for reading data from said memory cells;
- address lines for addressing said memory cells;
- and
- a switching unit having an active state in which said switching unit inverts a signal on a line selected from the group consisting of said data line and said address lines, said switching unit having an inactive state in which said switching unit leaves the signal unchanged,
- said active state and said inactive state defining states;
- said digital memory having a first operating mode, in which said switching unit is in the same one of said states for writing data to said memory cells and for reading data from said memory cells;
- and
- said digital memory having a second operating mode, in which said switching unit is in one of said states for writing data to said memory cells and is in another one of said states for reading data from said memory cells.
7 more elements
A method of operating a digital memory, which comprises:
- providing a digital memory with a first operating mode and a second operating mode;
- while in the first operating mode, writing data to the digital memory using a first address;
- while in the first operating mode, reading the data from the digital memory using the first address, the read data being in an unchanged logic state;
- while in a second operating mode, writing data to the digital memory using a second address;
- and
- while in the second operating mode, reading the data from the digital memory using the second address, the read data being in an inverted logic state.
3 more elements
Dependencies are inferred from the claim text.