Method of operating EEPROM memory cells having transistors with thin gate oxide and reduced disturb
AssigneeLattice Semiconductor Corporation
InventorsRobert H. Tu, Sunil D. Mehta
Life of this patent
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Abstract
An improved process of programming and erasing an EEPROM memory cell in an array of identical cells uses a reduced voltage on the write transistor of the cell to be programmed or erased and at the same time applies smaller voltages across the relatively thin oxides of the write transistors of the other cells in the array so as to reduce oxide leakage and damage in those cells but without disturbing the information stored in those cells. The result is the ability to scale down the size of the EEPROM memory cell allowing enhanced economies and permitting faster program, erase and reading speeds.
Claims29
A process of operating a first memory cell in a memory array, the memory array including the first memory cell and a second memory cell in the same row of the memory array as the first memory cell, each of the memory cells in the array having a write transistor comprising a write gate, a write source, a write drain, and a write gate oxide, each of the memory cells having a sense transistor comprising a sense floating gate and a sense gate oxide, and each of the memory cells having a tunnel diode coupled at its first terminal to the write source and at its second terminal to the sense floating gate, the write transistors in the first memory cell and the second memory cell being coupled at their write drains, the process of operating the first memory cell comprising the acts of:
- applying a voltage Vpp to the first memory cell write gate and to the first memory cell write drain;
- programming the first memory cell by removing electrons from the first memory cell's sense floating gate in response to the voltage Vpp;
- generating a voltage Vpp−Vmax where Vmax is a voltage less than or equal to the maximum voltage which can be applied across the second memory cell write gate oxide without causing damage to the second memory cell write gate oxide or causing substantial leakage through the second memory cell write gate oxide;
- applying the voltage Vpp−Vmax to the second memory cell write gate and, in response to the voltage Vpp applied to the first memory cell write transistor, applying the voltage Vpp to the second memory cell write drain;
- generating across the second memory cell write gate oxide a voltage less than or equal to Vmax in response to said applying the voltage Vpp−Vmax;
- and
- generating a voltage less than the voltage Vpp−Vmax at the second terminal of the second memory cell tunnel diode in response to the voltages Vpp and Vpp−Vmax applied to the second memory cell write transistor, the voltage generated being insufficient to program or erase the second memory cell sense transistor.
Dependencies are inferred from the claim text.