US 6,208,558 B1Granted

Acceleration circuit for fast programming and fast chip erase of non-volatile memory

AssigneeAdvanced Micro Devices, Inc.

InventorsJohnny Chen, Tiao-Hua Kuo, Nancy Leong

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Abstract

An acceleration circuit for fast programming and fast chip erase of a non-volatile memory array (46) comprises an acceleration input (2) coupled to a triggering circuit (4) which is capable of generating fast program and fast chip erase commands. In an embodiment, the triggering circuit (4) comprises a high voltage detector (6), which is coupled to the acceleration input (2), and a logic circuit (8), which is coupled to the high voltage detector (6) and has a plurality of command write inputs (10). In a further embodiment, the acceleration voltage is reduced by a regulator (52) to generate a regulated voltage, which is supplied to the memory cells (72a, 72b, 74a, 74b, . . . ) in fast program and fast chip erase modes.

Claims24

Dependent claims

In a non-volatile memory comprising at least one array of memory cells arranged in a plurality of rows and a plurality of columns, a plurality of word lines coupled to the respective rows of the memory cells, a plurality of bit lines coupled to the respective columns of the memory cells, each of the memory cells comprising a source and a drain, the bit lines arranged in a plurality of sets, and an internal voltage supply pump for generating an internal pump voltage to provide a pump current for programming the memory cells on the bit lines one set at a time in an embedded program mode, an acceleration circuit for fast programming of the memory cells comprising:

(a) an acceleration input for providing an acceleration voltage to supply a current for programming the memory cells on all sets of the bit lines at a time in a fast program mode, the acceleration voltage being greater than the internal pump voltage;
and
(b) a triggering circuit, coupled to the acceleration input, for causing the acceleration voltage to be supplied to the memory cells on all sets of the bit lines at a time in response to a presence of the acceleration voltage at the acceleration input.

In a non-volatile memory comprising at least one array of memory cells arranged in a plurality of rows and a plurality of columns, a plurality of word lines coupled to the respective rows of the memory cells, a plurality of bit lines coupled to the respective columns of the memory cells, each of the memory cells comprising a source and a drain, the columns of the memory cells arranged in a plurality of sets, and an internal voltage supply pump for generating an internal pump voltage to provide a pump current for programming the memory cells one set of columns at a time in an embedded program mode, an acceleration circuit comprising:

(a) an acceleration input for providing an acceleration voltage greater than the internal pump voltage either to program the memory cells in all sets of the columns at a time in a fast program mode, or to erase the memory cells in all sets of the columns at a time in a fast chip erase mode in which fast preprogramming, fast erase and fast weak programming operations are performed on the memory cells;
(b) a triggering circuit coupled to the acceleration input, for causing the acceleration voltage to be supplied to the memory cells in all sets of the columns at a time in response to a presence of the acceleration voltage at the acceleration input, the triggering circuit comprising:
a plurality of command inputs, including
(A) a program command write input for receiving a program command;
(B) an erase command write input for receiving an erase command:;
(C) an erase select command input for receiving an erase select command;
and
(D) a weak program command input for receiving a weak program command;
(ii) a high voltage detector coupled to the acceleration input, for generating an acceleration voltage indicator signal in response to detecting the acceleration voltage at the acceleration input;
and
(c) a regulator, coupled to the acceleration input, for regulating the acceleration voltage to generate a drain voltage to program the memory cells selected to be programmed in the fast program mode.

8 more elements

Dependencies are inferred from the claim text.