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US 6,208,555 B1Granted
Negative resistance memory cell and method
AssigneeMicron Technology, Inc.
InventorWendell P. Noble
Life of this patent
Estimating the term…
Abstract
A SRAM memory cell including two tunnel diodes coupled in series and a MOS FET. A first of the tunnel diodes may be formed in a shallow trench. A second of the tunnel diodes may be formed in a source or drain contact region of the FET. The FET acts as a pass gate to allow data to be read from or written to the memory cell when the gate of the FET is biased to turn the FET ON. The FET otherwise acts to prevent the datum stored in the memory cell from being altered when the FET is turned OFF. The memory cell may be formed to be unusually compact and has a reduced power supply requirements compared to conventional SRAM memory cells. As a result, a compact and robust SRAM having reduced standby power requirements is realized.
Claims53
A memory cell comprising:
- a substrate including silicon;
- a first negative resistance device formed in a shallow trench and having first and second electrodes, the first electrode being coupled to a first reference voltage;
- a second negative resistance device formed on the substrate, the second negative resistance device having a first electrode coupled to a second reference voltage and a second electrode coupled to the second electrode of the first negative resistance device;
- and
- a switching element formed on the substrate and having a control electrode coupled to a first selection line, a first current-carrying electrode coupled to the second electrodes of the first and second negative resistance devices, and a second current-carrying electrode coupled to a second selection line.
2 more elements
A memory device having an address bus and a data terminal, comprising:
- an array of memory cells formed on a substrate including silicon, the memory cells arranged in rows and columns, each of the rows having a word line and each of the columns having a bit line;
- a row address circuit coupled to the address bus for activating the word line in the array corresponding to a row address applied to the row address circuit through the address bus;
- a column address circuit coupled to the address bus for coupling an I/O line for the array to the bit line corresponding to a column address applied to the column address circuit through the address bus;
- and
- a sense amplifier having an input coupled to a data line and an output coupled to the data terminal of the memory device, wherein each memory cell comprises:
- a first negative resistance device having a first electrode coupled to a first reference voltage and formed in a shallow trench;
- a second negative resistance device having a first electrode coupled to node that is coupled to a second electrode of the first negative resistance device and a second electrode coupled to a second reference voltage;
- and
- a switching element having a control electrode coupled to one of the word lines, a first current-carrying electrode coupled to the node and a second current-carrying electrode coupled to one of the bit lines, the first current-carrying electrode formed in the substrate adjacent the shallow trench.
6 more elements
A memory comprising:
- addressing means having a first set of terminals coupled to a first external port and a second set of terminals coupled to a memory array, the addressing means for targeting one or more memory cells within the memory array;
- and
- data conditioning means coupled to a second external port and to the memory array, the data conditioning means for reading data from or writing data to the one or more targeted memory cells, wherein each memory cell comprises:
- first negative resistance means having a first terminal coupled to a first reference voltage and a second terminal coupled to a node, the first negative resistance means formed in a shallow trench;
- second negative resistance means having a first terminal coupled to the node and a second terminal coupled to a second reference voltage;
- and
- switching means having a control electrode coupled to a first selection line, a first current-carrying electrode coupled to the node and a second current-carrying electrode coupled to a second selection line.
4 more elements
A computer system, comprising:
- a processor having a processor bus;
- an input device coupled to the processor through the processor bus and adapted to allow data to be entered into the computer system;
- an output device coupled to the processor through the processor bus and adapted to allow data to be output from the computer system;
- and
- a memory device coupled to the processor through the processor bus, the memory device comprising:
- at least one array of memory cells arranged in rows and columns, each of the rows having a word line and each of the columns having a bit line;
- a row address circuit adapted to receive and decode a row address, and select a row of memory cells corresponding to the row address;
- a column address circuit adapted to couple the bit line for the column corresponding to a column address to an I/O line to receive or apply data to one of the memory cells in the selected row corresponding to a column address;
- and
- a data path circuit adapted to couple data between an external data terminal and each of the bit lines for respective columns, the data path circuit including a sense amplifier having an output coupled to the external data terminal of the memory device and an input, wherein each of the memory cells comprises first and second negative resistance devices formed from silicon and coupled together in series between first and second reference voltages and a switching device having a first current-carrying electrode coupled to a node between the first and second negative resistance devices, a control electrode coupled to one of the word lines and a second current-carrying electrode coupled to one of the bit lines.
7 more elements
A method of operating a memory device comprising:
- coupling a first voltage to a gate of a MOS FET that is part of a memory cell to turn the FET ON;
- and
- sensing a voltage at a node that is coupled to an anode of a first tunnel diode, a cathode of a second tunnel diode and a first current-carrying electrode of the MOS FET, the voltage representing a datum stored in the memory cell.
A memory cell formed in a substrate, comprising:
- a switching element having a source/drain region;
- a first negative resistance device formed in a shallow trench adjacent to the switching element, the first negative resistance device having an electrode electrically coupled to the source/drain region of the switching element;
- and
- a second negative resistance device formed in the source/drain region of the switching element.
1 more element
An array of memory cells formed in a semiconductor substrate, comprising:
- a plurality of pairs of memory cells, each pair sharing a common sense node and formed in a common active region;
- and
- a plurality of shallow trenches formed in the substrate to isolate the active regions of the plurality of pairs of memory cells,
- wherein each memory cell of the pair includes a switch coupling a respective source/drain region to the common sense node, a first negative resistance device formed in the respective source/drain region, and a second negative resistance device having an electrode electrically coupled to the respective source/drain region, the second negative resistance devices of two adjacent pairs of memory cells formed in the shallow trench isolating the adjacent active regions.
1 more element
Dependencies are inferred from the claim text.