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US 6,208,554 B1Granted
Single event upset (SEU) hardened static random access memory cell
AssigneeLockheed Martin Corporation
InventorsHo Gia Phan, Derwin Jallice, Bin Li, Joseph Hoffman
Life of this patent
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Abstract
A single event upset hardened memory cell to be utilized in static random access memories is disclosed. The single event upset hardened memory cell includes a first set of cross-coupled transistors, a second set of cross-coupled transistors, a first set of isolation transistors, and a second set of isolation transistors. The first and second sets of isolation transistors are coupled to the first and second set of cross-coupled transistors, respectively, such that two inversion paths are formed between the cross-coupled transistors and the isolation transistors.
Claims35
A single event upset hardened bi-stable circuit, comprising:
- a first set of two cross-coupled transistors and a second set of two cross-coupled transistors, wherein said cross-coupling is accomplished by connecting a gate of each transistor to a drain of another transistor in a same set;
- and
- a first set of isolation transistors and a second set of isolation transistors, wherein said first and second sets of isolation transistors are respectively connected to said first and second sets of cross-coupled transistors such that two inversion paths are formed including said two sets of cross-coupled transistors and said two sets of isolation transistors.
A single event upset hardened bi-stable circuit, comprising:
- a first transistor cross-coupled to a second transistor;
- a third transistor cross-coupled to a fourth transistor;
- a first isolation and a second isolation transistors connected in series between said first transistor and said third transistor to form a first inversion path with said second transistor and said fourth transistor;
- a third isolation and fourth isolation transistors connected in series between said second transistor and said fourth transistor to form a second inversion path with said first transistor and said third transistor.
1 more element
A single event upset hardened bi-stable circuit, comprising:
- a first transistor, a second transistor, a third transistor, and a fourth transistor connected in series;
- and
- a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor connected in series, wherein a gate of said third transistor and said seventh transistor is connected to a high voltage and a gate of said second transistor and said sixth transistor is connected to a low voltage, wherein a gate of said first transistor is connected to a node between said fifth transistor and said sixth transistor, wherein a gate of said fifth transistor is connected to a node between said first transistor and said second transistor, wherein a gate of said fourth transistor is connected to a node between said seventh transistor and said eighth transistor, wherein a gate of said eighth transistor is connected to a node between said third transistor and said fourth transistor.
A memory device, comprising:
- a sense amplifier;
- an addressing circuitry having a row decoder and a column decoder;
- an array of wordlines and complementary bit line pairs, coupled to said sense amplifier and said addressing circuitry;
- a plurality of memory cells located at an intersection of each of said wordlines and said bit line pairs, wherein each of said plurality of memory cells has a single event upset hardened bi-stable circuit that includes:
- a first set of two cross-coupled transistors and a second set of two cross-coupled transistors, wherein said cross-coupling is accomplished by connecting a gate of each transistor to a drain of another transistor in a same set;
- and
- a first set of isolation transistors and a second set of isolation transistors, wherein said first and second sets of isolation transistors are respectively connected to said first and second sets of cross-coupled transistors such that two inversion paths are formed including said two sets of cross-coupled transistors and said two sets of isolation transistors.
4 more elements
An apparatus, comprising:
- an electronic system;
- and
- a memory device having a plurality of memory cells, wherein each of said plurality of memory cells has a single event upset hardened bi-stable circuit that includes:
- a first set of two cross-coupled transistors and a second set of two cross-coupled transistors, wherein said cross-coupling is accomplished by connecting a gate of each transistor to a drain of another transistor in a same set;
- and
- a first set of isolation transistors and a second set of isolation transistors, wherein said first and second sets of isolation transistors are respectively connected to said first and second sets of cross-coupled transistors such that two inversion paths are formed including said two sets of cross-coupled transistors and said two sets of isolation transistors.
3 more elements
Dependencies are inferred from the claim text.