Circuit and method for biasing the charging capacitor of a semiconductor memory array

#This invention relates in general to the field of memory devices, and more particularly to a circuit and method for biasing the charging capacitor of a semiconductor memory array.

#The peripheral circuitry of a semiconductor memory array often includes a charging capacitor coupled between a reference voltage and ground. The stored charge of the charging capacitor is passed through the word line decoding circuits and word line detection circuits to charge the reference capacitors of the memory cells of the word line or word lines selected by the decoding and detection circuits. Because the charging capacitor must provide a reference voltage to each word line in the memory array, the charging capacitor often has a large surface area and is prone to failure upon the application of a sufficiently high voltage differential across the plates of the charging capacitor. The charging capacitor may also be coupled to ground from an oxide layer common to other components of the semiconductor memory array, including the gates of transistors in the memory. As a result, failure in these other components also connected between the common oxide layer and ground will result in failure of the charging capacitor as well.

#Conventionally, the charging capacitor is biased during operation and testing by placing a reference voltage at the anode of the capacitor and grounding the cathode of the capacitor. During the testing of DRAM semiconductor memories, the voltage level applied to the word lines of the memory array is raised for an extended period. During burn-in testing, for example, the voltage applied to each word line is elevated from a normal level to a higher voltage for an extended period, possibly 20 hours or longer. Other testing modes are possible, including operating-life testing. As compared to the voltage applied during burn-in testing, the voltage applied to the word lines during operating-life testing is lower but is applied for a longer period, possibly 1000 hours or longer. Burn-in testing and operation-life testing are necessary to insure an adequate length of operating life for the semiconductor memory device. Each of these testing modes employs accelerated operating conditions over shorter period to simulate the effects of normal operating conditions over a longer period.

#A more complete understanding of the present invention and advantages thereof may be acquired by referring to the following description taken in conjunction with the accompanying drawing in which like reference numbers indicate like features, and wherein:

#FIG. 1 is a diagram of the semiconductor memory array of the present invention; and

#FIG. 2 is a diagram of the charging capacitor of the present invention.

#Referring to FIG. 1, a dynamic random access memory (DRAM) device, indicated generally at 10, is provided. DRAM 10 includes a plurality of memory cells 12, each at the intersection of a word line 14 and a bit line 16. Each memory cell 12 includes a MOS transistor 18. The gate of each MOS transistor 18 is coupled to a word line 14 and the drain of each MOS transistor 18 is coupled to a bit line 16. The source of each MOS transistor 18 is coupled to ground through an access capacitor 20. Data is stored in each memory cell 12 in the form of a charge stored in access capacitor 20. A logic 1 may be stored by charging access capacitor 20 to a higher voltage and a logic 0 may be stored by discharging access capacitor 20 to a lower voltage. Each bit line 16 is coupled to a sense amplifier 22 and a column decoder 24.

#Each word line 14 is coupled to a word line selection circuit 26. Word line selection circuit 26 is coupled to a word line address decoder 28. The inputs of word line address decoder 28 are a plurality of word line inputs 30. Word line address decoder 28 decodes the word line inputs 30 and outputs an address to word line selection circuit 26, which energizes one of more of word lines 14 on the basis of the word line inputs 30 provided at the input of the word line selection circuit 26.

#Also coupled to the input of word line selection circuit 26 is the output of DRAM charge circuit 29. The purpose of charge circuit 29 is to hold a positive charge that can be passed through word line selection circuit 26 to any of word lines 14. When a word line 14 is selected during a READ or WRITE operation, the capacitive charge of charge circuit 29 is passed to the selected word line 14 to cause all the transistors 18 of the selected word line 14 to become conductive. Charge circuit 29 includes a charging capacitor 31 (not shown in FIG. 1).