One-time programmable poly-fuse circuit for implementing non-volatile functions in a standard sub 0.35 micron CMOS

A memory system comprising:

• an array of polycide fuse elements arranged in at least one row and a plurality of columns;
• an access control circuit for individually reading and programming each of the polycide fuse elements;
• a plurality of bit lines, wherein each of the columns of polycide fuse elements is connected to a corresponding one of the bit lines;
• a column decoder circuit configured to selectively couple one of the bit lines to the access control circuit in response to an address signal;
• and
• a row decoder circuit configured to selectively couple the polycide fuse elements in a row of the array between the corresponding one of the bit lines and a voltage supply terminal in response to an address signal.

A one-time programmable memory circuit fabricated on a chip, the memory circuit comprising:

• a VDD supply terminal configured to supply a VDD supply voltage to core logic on the chip;
• a VIO supply terminal configured to provide a VIO supply voltage to input/output logic on the chip, wherein the VIO supply voltage is greater than the VDD supply voltage;
• a polycide fuse;
• and
• an access control circuit for programming and reading the polycide fuse, the access control circuit being configured to couple the VIO supply terminal to the polycide fuse during programming, the access control circuit further being configured to couple the VDD supply terminal to the polycide fuse during reading.