Memory module

A memory module comprising a plurality of memory chips scribed from a semiconductor wafer and mounted on a module board which is formed with a plurality of external connection terminals for carrying signals to and from the plurality of memory chips,

• wherein the module board is formed with two rows of pads, equal number of the memory chips are disposed on the module board at opposite sides of the row of pads, and the pads in one row on the module board are connected to the pads on the memory chips more remote from the row of the pads by using bonding wires.

A memory module comprising a plurality of memory chips scribed from a semiconductor wafer and mounted on a module board which is formed with a plurality of external connection terminals for carrying signals to and from the plurality of memory chips,

• wherein the module board is formed with a plurality of pads formed in correspondence to the plurality of memory chips, the memory chips are formed with a plurality of pads in correspondence to the pads on the module board, and the corresponding pads on the module board and the pads of the memory chips are interconnected by way of electrically conductive material.

A memory module comprising a plurality of memory chips scribed from a semiconductor wafer and mounted on a module board which is formed with a plurality of external connection terminals for carrying signals to and from the plurality of memory chips,

• wherein the memory chips formed on the semiconductor wafer are scribed in a group of two or more before being mounted on the module board, and
• wherein the memory chips in a group of plural chips are scribed and mounted on the module board by the use of bonding wires.

A memory module comprising a plurality of memory chips scribed from a semiconductor wafer and mounted on a module board which is formed with a plurality of external connection terminals for carrying signals to and from the plurality of memory chips,

• wherein the memory chips formed on the semiconductor wafer are scribed in a group of two or more before being mounted on the module board, and
• wherein the module hoard is formed with a plurality of pads in correspondence to the memory chips scribed in the group, the memory chips are formed with a plurality of pads at locations corresponding to the pads on the module board, and the corresponding pads on the module board and the memory chips are interconnected by way of electrically conductive material.

A memory module comprising a plurality of memory chips scribed from a semiconductor wafer and mounted on a module board which is formed with a plurality of external connection terminals for carrying signals to and from the plurality of memory chips,

• wherein the module board is rectangular and formed with a plurality of recessed portions in the direction of thickness along opposed side edges to define external connection terminals by forming the surface of the recessed portions and the peripheries thereof with electrically conductive material.

A memory module comprising a plurality of memory chips scribed from a semiconductor wafer and mounted on a module board which is formed with a plurality of external connection terminals for carrying signals to and from the plurality of memory chips,

• wherein the module board is formed with the external connection terminals on the opposite surface to the memory chip mounting surface.

A memory module comprising a plurality of memory chips scribed from a semiconductor wafer and mounted on a module board which is formed with a plurality of external connection terminals for carrying signals to and from the plurality of memory chips,

• wherein the number of address terminals included in the plurality of external connection terminals formed in the module board is equalized to the number of address terminals of the memory chips.

A memory module comprising a plurality of memory chips scribed from a semiconductor wafer and mounted on a module board which is formed with a plurality of external connection terminals for carrying signals to and from the plurality of memory chips,

• wherein each of the memory chips has a plurality of control terminals including write enable, output enable, RAS and CAS terminals, and all of the control terminals except the CAS terminal are commonly connected to all of the memory chips.