Translation lookaside buffer (TLB) including fast hit signal generation circuitry

A memory unit, comprising:

• a set of n driver circuits for driving n signals upon n signal lines;
• a data array coupled to the n signal lines and configured to store a plurality of data items, wherein the plurality of data items are accessed by the n signals driven upon the n signal lines, and wherein assertion of one of the n signals indicates the presence of a requested data item within said plurality of data items within the data array;
• a hit circuit comprising a set of n driver cells coupled to a first bit line and a second bit line, wherein each of the n driver cells of the hit circuit is coupled to receive a different one of the n signals and configured to drive the first bit line toward a first voltage level with a first drive strength and the second bit line toward a second voltage level when the received one of the n signals is asserted;
• a miss circuit coupled to the first and second bit lines, wherein the miss circuit is configured to drive the first bit line toward the second voltage level with a second drive strength, and wherein the second drive strength is less than the first drive strength such that a differential voltage developed between the first and second bit lines is indicative of the presence or absence of the requested data item within the data array;
• a sense amplifier coupled to the first and second bit lines and configured to produce an output signal dependent upon the differential voltage developed between the first and second bit lines;
• and
• an output driver coupled to receive the output signal produced by the sense amplifier and configured to produce an output signal indicative of the presence or absence of the requested data item within the data array.

A cache unit, comprising:

• a cache memory for storing a plurality of data items and corresponding physical addresses, wherein the cache memory is configured to produce one of the plurality of data items when provided with the corresponding physical address of the data item;
• and
• a translation lookaside buffer (TLB) coupled to the cache memory and adapted for storing a plurality of virtual addresses and corresponding physical addresses, wherein the TLB is coupled to receive a virtual address and configured to produce a physical address corresponding to the virtual address and to provide the physical address to the cache memory, wherein the TLB comprises:
• a data array for storing n page frame addresses, wherein the n page frame addresses are accessed by n signals, and wherein assertion of one of the n signals indicates the presence of a page frame address corresponding to a virtual page number portion of the virtual address within the data array;
• and
• a hit circuit comprising n driver cells coupled to a first bit line and a second bit line, wherein each of the n driver cells is coupled to receive a different one of the n signals and configured to drive the first bit line toward a first voltage level and the second bit line toward a second voltage level when the received one of the n signals is asserted such that a differential voltage is developed between the first and second bit lines, and wherein the differential voltage is indicative of the presence of the page frame address corresponding to the virtual page number portion of the virtual address within the data array.

A processor, comprising:

• a cache unit for storing a plurality of data items, wherein the cache unit is configured to produce a data item when provided with a virtual address corresponding to a physical address of the data item, and wherein the cache unit comprises:
• a cache memory for storing the plurality of data items and corresponding physical addresses, wherein the cache memory is configured to produce one of the plurality of data items when provided with the corresponding physical address of the data item;
• and
• a translation lookaside buffer (TLB) coupled to the cache memory and adapted for storing a plurality of virtual addresses and corresponding physical addresses, wherein the TLB is coupled to receive the virtual address provided to the cache unit and configured to produce the physical address corresponding to the virtual address, and to provide the physical address to the cache memory, wherein the TLB comprises:
• a data array for storing n page frame addresses, wherein the n page frame addresses are accessed by n signals, and wherein assertion of one of the n signals indicates the presence of a page frame address corresponding to a virtual page number portion of the virtual address within the data array;
• and
• a hit circuit comprising n driver cells coupled to a first bit line and a second bit line, wherein each of the n driver cells is coupled to receive a different one of the n signals and configured to drive the first bit line toward a first voltage level and the second bit line toward a second voltage level when the received one of the n signals is asserted such that a differential voltage is developed between the first and second bit lines, and wherein the differential voltage is indicative of the presence of the page frame address corresponding to the virtual page number portion of the virtual address within the data array.

A computer system, comprising:

• a processor for executing instructions, including:
• a cache unit for storing a plurality of data items, wherein the cache unit is configured to produce a data item when provided with a virtual address corresponding to a physical address of the data item, and wherein the cache unit comprises:
• a cache memory for storing the plurality of data items and corresponding physical addresses, wherein the cache memory is configured to produce one of the plurality of data items when provided with the corresponding physical address of the data item;
• and
• a translation lookaside buffer (TLB) coupled to the cache memory and adapted for storing a plurality of virtual addresses and corresponding physical addresses, wherein the TLB is coupled to receive the virtual address provided to the cache unit and configured to:
• (i) produce a physical address corresponding to the virtual address, and (ii) provide the physical address to the cache memory, wherein the TLB comprises:
• a data array for storing n page frame addresses, wherein the n page frame addresses are accessed by n signals, and wherein assertion of one of the n signals indicates the presence of a page frame address corresponding to a virtual page number portion of the virtual address within the data array;
• and
• a hit circuit comprising n driver cells coupled to a first bit line and a second bit line, wherein each of the n driver cells is coupled to receive a different one of the n signals and configured to drive the first bit line toward a first voltage level with a first drive strength and the second bit line toward a second voltage level when the received one of the n signals is asserted such that a differential voltage is developed between the first and second bit lines, and wherein the differential voltage is indicative of the presence of the page frame address corresponding to the virtual page number portion of the virtual address within the data array.