Techniques for storing digital data in an analog or multilevel memory

An integrated circuit comprising:

• an array of memory cells;
• a write circuit to store an information provided at an analog input and a digital input of the integrated circuit into the memory cells, wherein the information provided at the analog input is in an analog form and at the digital input is in digital form;
• and
• a multiplexer, coupled between the analog input and the write circuit, and the digital input and the write circuit, to selectively couple the analog input to the write circuit or the digital input to the write circuit, wherein the information provided at the analog input is sampled at a sampling frequency and each sample is stored in one memory cell, wherein the sampling frequency is user-selectable by providing a digital command to the integrated circuit.

An integrated circuit comprising:

• a plurality of memory cells;
• a write circuit coupled to the memory cells;
• and
• a read circuit to determine a threshold voltage stored in individual memory cells, and to provide an analog equivalent of the stored threshold voltage at an analog output or to provide a digital equivalent of the stored threshold voltage at a digital output, wherein individual memory cells are configurable by the write circuit to store more than two different threshold voltage levels, and the read circuit provides a sequence of analog equivalents to the analog output at a user-selected playback frequency.

An integrated circuit comprising:

• an array of multilevel memory cells;
• a write circuit coupled to store data in the array of multilevel memory cells;
• a digital reference generator, receiving digital data and converting the digital data into an analog equivalent form, wherein the analog equivalent form is provided to the write circuit, and the digital reference generator comprises:
• a bias voltage generator generating a plurality of bias voltages;
• and
• a digital data input circuit generating the analog equivalent form of the digital data by selecting combinations of the plurality of bias voltages.

An integrated circuit comprising a digital reference generator comprising:

• a first impedance coupled between a first supply line and a first output line;
• a second impedance coupled between the first output line and a first node;
• a third impedance coupled between the first node and a second output line;
• a fourth impedance coupled between the second output line and a second supply line;
• a first switch coupled in parallel with the second impedance;
• and
• a second switch coupled in parallel with the third impedance.

A method of storing information in a memory comprising:

• providing an analog signal at an analog signal input;
• providing digital data at a digital signal input;
• sampling the analog signal input at a sampling frequency;
• storing samples of the analog signal in an array of memory cells, wherein a memory cell holds at least one sample of the analog signal;
• and
• storing the digital data in the array of memory cells, wherein a memory cell holds at least a bit of the digital data, wherein storing the digital data comprises:
• erasing a sector of memory cells;
• writing the digital data in the sector of memory cells;
• and
• writing a digital value in each memory cell of the sector not written with the digital data.