Pulse compressor for doppler tolerant radar

A digital finite impulse response filter for pulse compressing radar returns for radar systems having means for generating a radar transmission signal having broad Doppler tolerant pulses such as linear frequency modulated pulses and frequency modulated pulses, said filter comprising

• weighting means for storing a plurality of weighting coefficients defined by sampling said radar signal at a desired sample rate, said weighting means including real weighting means for storing a plurality of real coefficients defined by sampling said radar signal at a desired sample rate, and imaginary weighting means for storing a plurality of imaginary coefficients defined by sampling a quadrature phase version of said radar signal at the desired sample rate;
• shift register means for sequentially introducing digitized return samples of the radar returns into each of a plurality of storage positions within said shift register means, each such storage position being associated with one of the weighting coefficients;
• a plurality of digital multipliers in one-to-one correspondence with the shift register means storage positions, each of said multipliers being arranged to output a product of the return sample currently stored in the corresponding storage position multiplied by the associated weighting coefficient, whereby each of said digital multipliers corresponds with a corresponding one of the weighting coefficients, each of said multipliers being arranged to output a product of a corresponding weighting coefficient multiplied by a most recent digitized return sample of the radar return;
• and
• summing means responsive to said multipliers for outputting a sum of all the multiplier products, said summing means including summing shift register means having a plurality of storage positions in one-to-one correspondence with the digital multipliers and a plurality of two-input digital summers arranged such that a number stored in each summing shift register means storage position is summed with the output of said digital multiplier associated with an adjacent summing shift register means storage position before being shifted to said adjacent storage position, said weighting means, shift register means, multipliers and summing means being of sufficient resolution to permit arbitrary use of any pulse length, bandwidth and modulation combination.