Delay cell with controlled output amplitude

A ring oscillator comprising:

• a plurality of delay cells with controlled output amplitude each comprising a fast delay stage including a differential amplifier for connection to a differential input, a slow delay stage comprising a differential amplifier connected in parallel with the fast delay stage differential amplifier and having capacitance means for setting a delay amount, a current source developing a bias current, a current switch connected between the current source and the fast delay stage and the slow delay stage to switch the bias current between the fast delay stage and the slow delay stage, and an output circuit connected to the fast and slow delay stages for developing a differential output stage delayed relative to the differential input responsive to a ratio between fast delay stage current and slow delay stage current and including an isolation circuit for isolating the capacitance means from the fast delay stage;
• means connecting the plurality of delay cells to provide a ring, the connecting means connecting the differential input of each delay cell to the differential output of another delay cell, wherein an odd number of said connections provide inversions;
• and
• control means connected to the current switch of each delay cell to control cell delay and thus oscillator frequency.

A delay circuit with controlled output amplitude comprising:

• a fast delay stage comprising a differential amplifier for connection to a differential input;
• a slow delay stage comprising a differential amplifier connected in parallel with the fast delay stage differential amplifier having capacitance means for setting a delay amount;
• a current source developing a bias current;
• a current switch connected between the current source and the fast delay stage and the slow delay stage to switch the bias current from between the fast delay stage and the slow delay stage;
• and
• an output circuit connected to the fast and slow delay stages for developing a differential output delayed relative to the differential input responsive to a ratio between fast delay stage current and slow delay stage current, the output circuit comprising a pair of load resistors connected between a voltage source and the parallel connected fast delay stage and slow delay stage and a cascode circuit connected between the slow delay stage and the load resistors to isolate capacitance of the slow delay stage from the fast delay stage.

A ring oscillator comprising:

• a plurality of delay cells with controlled output amplitude each comprising a fast delay stage including a differential amplifier for connecting to a differential input, a slow delay stage comprising a differential amplifier connected in parallel with the fast delay stage differential amplifier and having capacitance means for setting a delay amount, a current source developing a bias current, a current switch connected between the current source and the fast delay stage and the slow delay stage to switch the bias current between the fast delay stage and the slow delay stage, and an output circuit connected to the fast and slow delay stages for developing a differential output delayed relative to the differential input responsive to a ratio between fast delay stage current and slow delay stage current, the output circuit comprising a pair of load resistors connected between a voltage source and the parallel connected fast delay stage and slow delayed stage and a cascode circuit connected between the slow delay stage and the load resistors to isolate capacitance of the slow delay stage from the fast delay stage;
• means connecting the plurality of delay cells to provide a ring, the connecting means connecting the differential input of each delay cell to the differential output of another delay cell, wherein an odd number of said connections provide inversions;
• and
• control means connected to the current switch of each delay cell to control cell delay and thus oscillator frequency.