Level shift circuit with low voltage operation
AssigneeSony Corporation
InventorHideki Arakawa
Life of this patent
Estimating the term…
Abstract
A level shift circuit capable of performing a low voltage operation without increasing the power consumption is described. A charge pump type level shift circuit incorporates NMOS transistors having well-in-well structures, where the potential of these wells are designed to rise along with the rise of the output voltage. The level shift circuit is capable of eliminating a back-bias effect and can lower the power source voltage to as low as 2V.
Claims23
A level shift circuit for shifting a first voltage applied to an input terminal to a second, shifted voltage higher than the first voltage and then outputting said shifted voltage to an output terminal, comprising:
- a first Field Effect Transistor (FET) of a first conductive type, having a first terminal connected to said input terminal and a second terminal connected to said output terminal;
- a second FET of the first conductive type, having a first terminal connected to a capacitance element, a second terminal connected to said output terminal, and a gate connected to said capacitance element;
- a third FET of the first conductive type, having a first terminal connected to the gate of said second FET, a second terminal connected to a voltage source, and a gate connected to said output terminal;
- a well potential adjustment circuit connected to said output terminal and having a first well of the first conductive type;
- said second FET having a second well of a second conductive type being formed in a first well of said second FET thereby being formed as a well-in-well type FET,
- wherein a pulse signal is applied to said capacitance element for the shifting of said first voltage, and
- said well potential adjustment circuit raising the potential of said second well in response to said second voltage at said output terminal.
A level shift circuit for shifting a first voltage applied to an input terminal to a second, shifted voltage higher than the first voltage and then outputting said shifted voltage to an output terminal, comprising:
- a first Field Effect Transistor (FET) of a first conductive type, having a first terminal connected to said input terminal and a second terminal connected to said output terminal;
- a second FET of the first conductive type, having a first terminal connected to a capacitance element, a second terminal connected to said output terminal, and a gate connected to said capacitance element;
- a third FET of the first conductive type, having a first terminal connected to the gate of said second FET, a second terminal connected to a voltage source, and a gate connected to said output terminal;
- said second FET having a second well of a second conductive type being formed in a first well of said second FET thereby being formed as a well-in-well type FET,
- wherein a pulse signal is applied to said capacitance element for the shifting of said first voltage, and
- a well potential adjustment circuit for raising the potential of said second well in response to said second voltage at said output terminal;
- wherein said well potential adjustment circuit comprises a resistor connected between said capacitance element and said second well of said second FET.
Dependencies are inferred from the claim text.