Pulse amplifier with low duty cycle errors
AssigneeMitel Semiconductor Limited
InventorBengt-Olov Andersson
Life of this patent
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Abstract
A low power pulse amplifier with low duty cycle errors. The amplifier provides several differential amplifier stages with a biasing and canceling network. To minimize duty cycle errors for large input signals, cascode transistors are added between the drains of the differential amplifiers and the outputs. The result is an amplifier having a duty cycle error of less than 5% at amplitude input ranges from 5 millivolts to the supply voltage.
Claims25
A pulse amplifier comprising a first input for receiving an input signal containing frequencies, a feedback input, an output, a plurality of fully differential amplifier stages between said inputs and said output, and an offset canceling feedback network between said output and said feedback input comprising an amplifier and a low pass filter having a cut-off frequency below said frequencies contained in said input signal.
A method of amplifying signal pulses containing frequencies, comprising the steps of passing said signal pulses through a succession of fully differential amplifier stages, and providing a feedback signal for said amplifier stages from an offset canceling network comprising an amplifier and a low pass filter having a cut-off frequency below said frequencies contained in said input signal.
A pulse amplifier comprising a first input for receiving an input signal containing frequencies, a feedback input, an output, a plurality of fully differential amplifier stages between said inputs and said output, each fully differential amplifier stage comprising first and second transistors forming a differential pair and having a common node, a pair of load transistors for said respective first and second transistors, and first and said cascode transistors in series with said first and second transistors for reducing the current through one of said first and second transistors driven into conduction in the presence of large input signals to limit the voltage swing of said common node, and an offset canceling feedback network between said output and said feedback input comprising an amplifier and a low pass filter having a cut-off frequency below said frequencies contained in said input signal.
A pulse amplifier comprising a first input for receiving an input signal containing frequencies, a feedback input, an output, a plurality of fully differential amplifier stages between said inputs and said output arranged to ensure more symmetrical delays in positive and negative directions of the input signals, each fully differential amplifier stage comprising first and second transistors forming a differential pair and having a common node, a pair of load transistors in parallel with said respective first and second transistors, and an offset canceling feedback network between said output and said feedback input comprising an amplifier and a low pass filter having a cut-off frequency below said frequencics contained in said input signal.
Dependencies are inferred from the claim text.