Synchronizing circuit for receiving an asynchronous input signal
AssigneeNEC Corporation
InventorShinichi Shionoya
Life of this patent
Estimating the term…
Abstract
A synchronizing circuit is of a master-slave type including a master latch and a slave latch. The master latch latches complementary signals at a rising edge of the clock signal. The slave latch latches the complementary signals output from the master latch at a falling edge of the clock signal. A capacitor is provided between the input node and the output node of each of the master latch and slave latch for assisting signal transition of the output node by the capacitive coupling between the input node and the output node having the same direction in the signal transition.
Claims15
A synchronizing circuit having two interconnected latch sections for latching an asynchronous input data to output a synchronous output data in synchrony with a clock signal,
- said synchronizing circuit comprising at least a first latch section having a first node, a second node, and a first capacitor connected between said first node and said second node for capacitive coupling therebetween,
- said first capacitor assisting a signal transition of said second node by using electric energy of a signal transition of said first node.
A synchronizing circuit for latching an asynchronous input data to output a synchronous output data in synchrony with a clock signal,
- said synchronizing circuit comprising a first latch section having a first node, a second node, and a first capacitor connected between said first node and said second node for capacitive coupling therebetween,
- said first capacitor assisting a signal transition of said second node by using electric energy of a signal transition of said first node,
- wherein each of said input data and output data includes a pair of complementary signals,
- wherein said first latch section includes a first gate section including a first NAND gate and a first OR gate having an output connected to an input of said first NAND gate and a second gate section including a second NAND gate and a second OR gate having an output connected to an input of said second NAND gate, and
- wherein said second latch section includes a third gate section including a first NOR gate and a first AND gate having an output connected to a first input of said first NOR gate, and a fourth gate section including a second NOR gate and a second AND gate having an output connected to a first input of said second NOR gate.
A synchronizing circuit for latching an asynchronous input data to output a synchronous output data in synchrony with a clock signal,
- said synchronizing circuit comprising a first latch section having a first node, a second node, and a first capacitor connected between said first node and said second node for capacitive coupling therebetween,
- said first capacitor assisting a signal transition of said second node by using electric energy of a signal transition of said first node,
- wherein each of said input data and output data includes a pair of complementary signals,
- wherein said first latch section includes a first gate section including a first NOR gate and a first AND gate having an output connected to an input of said first NOR gate and a second gate section including a second NOR gate and a second AND gate having an output connected to an input of said second NOR gate, and
- wherein said second latch section includes a third gate section including a first NAND gate and a first OR gate having an output connected to a first input of said first NAND gate, and a fourth gate section including a second NAND gate and a second OR gate having an output connected to a first input of said second NAND gate.
Dependencies are inferred from the claim text.