Differential signal generator

A differential signal generator comprising:

• a memory element having a true node and a complementary node;
• a first switch responsive to a first control input, the first switch configured to conditionally couple the true node of the memory element to a first reference voltage;
• a second switch responsive to a second control input, the second switch configured to conditionally couple the complementary node of the memory element to the first reference voltage;
• an input node coupled to the first control input and the second control input, such that when an input signal on the input node transitions from a first state to a second state, one of the first and second switches opens, and the other of the first and second switches closes;
• a third switch responsive to a third control input, the third switch being configured to conditionally couple the true node to a second reference voltage, the third control input being coupled to the input node such that the third switch is closed when the second switch is closed;
• and
• a fourth switch responsive to a fourth control input, the fourth switch being configured to conditionally couple the complementary node to the second reference voltage, the fourth control input being coupled to the input node such that the fourth switch is closed when the first switch is closed;
• wherein the memory element comprises a first latch having a first pair of cross-coupled inverters, and a second latch having a second pair of cross-coupled inverters.

A differential signal generator comprising:

• an input node, a true output node, and a complementary output node;
• a memory element coupled between the true output node and the complementary output node, wherein the memory element comprises a first latch coupled between the true output node and the complementary output node, and a second latch coupled between the true output node and the complementary output node;
• a voltage follower circuit having an input coupled to the input node, and having an output node coupled to the true output node;
• and
• an inverter circuit having an input coupled to the input node, and having an output node coupled to the complementary output node.

An integrated circuit comprising:

• a circuit element configured to receive a differential signal, the circuit element having a true input node and a complementary input node;
• and
• a differential signal generator comprising:
• a memory element having a true node coupled to the true input node of the circuit element, and having a complementary node coupled to the complementary input node of the circuit element, the memory element including at least one inverter having a PFET with a first drive strength and an NFET with a second drive strength, wherein the first and second drive strengths are not equal;
• a first switch responsive to a first control input, the first switch configured to conditionally couple the true node of the memory element to a first reference voltage;
• a second switch responsive to a second control input, the second switch configured to conditionally couple the complementary node of the memory element to the first reference voltage;
• and
• an input node coupled to the first control input and the second control input, such that when an input signal on the input node transitions from a first state to a second state, one of the first and second switches opens, and the other of the first and second switches closes.

A processor comprising:

• a circuit element configured to receive a differential signal, the circuit element having a true input node and a complementary input node;
• and
• a differential signal generator comprising:
• an input node, a true output node coupled to the true input node of the circuit element, and a complementary output node coupled to the complementary input node of the circuit element;
• a memory element coupled between the true output node and the complementary output node, the memory element including at least one inverter having a PFET with a first drive strength and an NFET with a second drive strength, wherein the first and second drive strengths are not equal;
• a voltage follower circuit having an input coupled to the input node, and having an output node coupled to the true output node;
• and
• an inverter circuit having an input coupled to the input node, and having an output node coupled to the complementary output node.

A method of generating a differential signal from a single ended signal, the method comprising:

• receiving a signal transition on an input node;
• responsive to the signal transition, closing a first switch coupled to a first side of a latch to change a logical state of a first output node;
• and
• responsive to the signal transition, opening a second switch coupled to a second side of the latch, wherein the latch comprises at least one pair of cross-coupled inverters having complementary transistors with unequal drive strengths.