US 6,208,184 B1 · Method and device for delaying selected transitions in a digital data stream

Abstract

A method and circuit are provided for delaying a transition in a digital data stream fed to a write head of a mass storage device by a certain time interval when the transition occurs at a clock phase following the one during which a preceding transition has occurred, for pre-compensating intersymbol nonlinear interference effects suffered when reading the stored data. The method includes feeding digital data stream to be stored and a clock signal to a first circuit and outputting a pair of digital streams from the first circuit. The first stream assumes a first logic value every time a transition of the input stream occurs during a clock phase not successive to a clock phase during which a transition of the input stream has occurred. The second stream assumes the first logic value every time a transition of the input stream occurs during a clock phase following a clock phase during which a transition has taken place in the input stream. The method also includes feeding the two digital streams and the clock signal to the inputs of a second circuit and outputting the digital data stream from the second circuit directed to the write head. The transitions immediately following a preceding transition are delayed by the pre-established time interval, by sampling the two digital streams with a pair of flip-flops, each of which is respectively timed by clock signals respectively delayed by a certain different time interval.

Claims34

Dependent claims

A method of delaying a transition in a digital data stream fed to a write head of a storage device by a predetermined time interval when the transition occurs at a clock phase following the clock phase during which a preceding transition has occurred, for pre-compensating for intersymbol nonlinear interference effects produced when reading stored data, the method comprising the steps of:

inputting the digital data stream and a clock signal to a first circuit;
outputting, from the first circuit, a pair of digital data streams including a first digital data stream which has a first logic value when a transition of the input digital data stream occurs during a clock phase that is not successive to a clock phase during which a transition of the input digital data stream has occurred, and a second digital data stream which has the first logic value when a transition of the input digital data stream occurs during a clock phase following a clock phase during which a transition has occurred in the input digital data stream;
feeding the first and second digital data streams and the clock signal to respective inputs of a second circuit;
and
outputting, from the second circuit, an output digital data stream directed to the write head, in which transitions immediately following a preceding transition are delayed by the predetermined time interval, by sampling the first and second digital data streams with a first pair of flip-flops, each of which is respectively timed by clock signals respectively delayed by a different time interval and such that the difference between the different time intervals is equal to the predetermined time interval, and recombining the first and second digital data streams output from the pair of flip-flops through a logic XOR gate into the output digital data stream.

2 more elements

A method of writing to a data storage device comprising the steps of:

determining whether a transition in a digital data stream occurs at a clock phase following a clock phase during which a preceding transition has occurred;
generating a first digital data stream having a first logic value when the transition of the digital data stream occurs during a clock phase that does not succeeed the clock phase during which a transition of the digital data stream occurred;
generating a second digital data stream having the first logic value when the transition of the digital data stream occurs during a clock phase that does succeed the clock phase during which the transition of the digital data stream occurred;
sampling the first digital data stream using a first delayed clock signal, and sampling the second digital data stream using a second delayed clock signal which is delayed by a different time interval than the first delayed clock signal, and such that a difference between the different time intervals is equal to a predetermined time interval;
combining the sampled first and second digital data streams as an output digital data stream;
and
writing the output digital data stream to the data storage device with transitions immediately succeeding a preceding transition being delayed by the predetermined time interval.

4 more elements

A disk drive comprising:

a data storage disk;
and
a write channel for carrying data to be written to the data storage disk, the write channel comprising
a write head for writing data to the data storage disk, and
a device for delaying a transition in a digital data stream fed to the write head by a predetermined time interval when the transition occurs at a clock phase following the clock phase during which a preceding transition h as occurred, the device comprising
a control circuit for detecting a first transition in the digital data stream that occurs during a clock phase succeeding an immediately preceding clock phase during which a transition has not occurred, for detecting a second transition in the digital data stream that occurs during a clock phase succeeding an immediately preceding clock phase during which a transition has occurred, and for outputting a first digital data stream corresponding to the first transition, and a second data digital stream corresponding to the second transition, and
a delay circuit for receiving the first and second digital data streams, for delaying the second transition by the predetermined time interval, and for outputting an output digital data stream.

4 more elements

Dependencies are inferred from the claim text.

Method and device for delaying selected transitions in a digital data stream

Life of this patent

Method and device for delaying selected transitions in a digital data stream

Life of this patent

Abstract

Claims34