Gated delay-locked loop for clock generation applications

A gated delay-locked loop that receives a reference clock having a frequency FREF and generates an output clock having a frequency FOUT=N·FREF that is synchronized in phase with the reference clock, the gated delay-locked loop composing:

• a gated oscillator including at least one delay element configured in a feedback loop that introduces a time delay Tdel to produce a delayed clock, the delay element having an input, said gated oscillator further including a multiplexer responsive to a gating pulse that selectively applies either a clock derived from the delayed clock or the reference clock to the feedback loop;
• a phase comparator for comparing the phase of a clock derived from the output clock to the phase of the reference clock and adjusting the time delay introduced by the at least one delay element to correct any detected phase difference;
• a first delay element that generates a first delayed clock coupled to a second delay element that generates the output clock, the output clock being coupled to said multiplexer;
• and
• a frequency adder coupled to the output of the multiplexer that adds the first delayed clock and either the reference clock or the output clock to derive a loop clock, and wherein the loop clock is coupled to the input of the first delay element.

A gated delay-locked loop that receives a reference clock having a frequency FREF and generates an output clock having a frequency FOUT=N·FREF that is synchronized in phase with the reference clock, the gated delay-locked loop comprising:

• a gated oscillator including at least one delay element configured in a feedback loop that introduces a time delay Tdel to produce a delayed clock, the delay element having an input, said gated oscillator further including a multiplexer responsive to a gating pulse that selectively applies either a clock derived from the delayed clock or the reference clock to the feedback loop;
• a phase comparator for comparing the phase of a clock derived from the output clock to the phase of the reference clock and adjusting the time delay introduced by the at least one delay element to correct any detected phase difference;
• and
• a first delay element that generates a first delayed clock coupled to a second delay element that generates the output clock, the output clock being coupled to said multiplexer;
• wherein the first and second delay elements are controlled by a voltage generated by the phase comparator, and wherein the gating pulse is applied to the multiplexer once every N cycles of the output clock to cause the multiplexer to select the reference clock for supply to the feedback loop, and wherein the multiplexer selects the output clock for supply to the feedback loop the remaining N−1 cycles.

A gated delay-locked loop that receives a reference clock having a frequency FREF and generates an output clock having a frequency FOUT=N·FREF that is synchronized in phase with the reference clock, the gated delay-locked loop comprising:

• a gated oscillator including at least one delay element configured in a feedback loop that introduces a time delay Tdel to produce a delayed clock, the delay element having an input, said gated oscillator further including a switch responsive to a gating signal that selectively applies either a clock derived from the delayed clock or the reference clock to the feedback loop;
• and
• a phase comparator for comparing the phase of a clock derived from the output clock to the phase of the reference clock and adjusting the time delay introduced by the at least one delay element to correct any detected phase difference;
• wherein the loop has a noise accumulation factor α = 1 - ( 1 - ϵ ) 2 ⁢ N 1 - ( 2 - ϵ ) 2 ,
• wherein N is a positive integer and ϵ = ω L ω REF
• is the ratio of the loop bandwidth to the frequency of the reference clock.

A gated delay-locked loop that receives a reference clock having a frequency FREF and generates an output clock having a frequency FOUT=N·FREF that is synchronized in phase with the reference clock, the gated delay-locked loop comprising:

• a gated oscillator including at least one delay element configured in a feedback loop that introduces a time delay Tdel to produce a delayed clock, the delay element having an input, said gated oscillator further including a multiplexer responsive to a gating pulse that selectively applies either a clock derived from the delayed clock or the reference clock to the feedback loop;
• a phase comparator for comparing the phase of a clock derived from the output clock to the phase of the reference clock and adjusting the time delay introduced by the at least one delay element to correct any detected phase difference;
• a first delay element that generates a first delayed clock coupled to a second delay element that generates the output clock, the output clock being coupled to said multiplexer;
• and
• a third delay element interposed between the multiplexer and the reference clock;
• wherein the third delay element is a fixed delay element that provides the multiplexer with sufficient time to switch states.

A method for generating an output clock having an output frequency FOUT equal to an integer N multiplied by a reference frequency FREF of a reference clock, the output clock having N cycles per cycle of the reference clock, the method comprising:

• (a) determining a current cycle of the output clock;
• (b) deriving a loop clock from the output clock if the current cycle is other than the Nth cycle;
• (c) deriving a loop clock from the reference clock if the current cycle is the Nth cycle;
• (d) delaying the loop clock;
• (e) deriving the output clock from the delayed loop clock;
• (f) incrementing the current cycle;
• and
• (g) repeating the method from step (a).

A method for generating an output clock having an output frequency FOUT equal to an integer N multiplied by a reference frequency FREF of a reference clock, the output clock having N cycles per cycle of the reference clock, the method comprising:

• (a) determining a current cycle of the output clock;
• (b) providing the output clock to a frequency adder if the current cycle is other than the Nth cycle;
• (c) providing the reference clock to the frequency adder if the current cycle is the Nth cycle;
• (d) providing a delayed loop clock to the frequency adder;
• (e) deriving the loop clock from the delayed loop clock and either the output clock or the reference clock;
• (f) delaying the loop clock to obtain the delayed loop clock;
• (g) delaying the delayed loop clock to obtain the output clock;
• (h) incrementing the current cycle;
• and
• (i) repeating the method from step (a).

A gated oscillator that receives a reference clock having a frequency FREF and generates an output clock having a frequency FOUT=N·FREF that is synchronized in phase with the reference clock, the oscillator comprising:

• a switch that is responsive to a gating signal to switch between the reference clock and the output clock;
• a frequency adder coupled to the output of the switch that derives a loop clock from the clock output by the switch and a delayed loop clock;
• and
• at least one delay element coupled to the output of the frequency adder to produce the delayed loop clock and the output clock.