Phase-locked loop circuit

A phase-locked loop circuit, including:

• a programmable ring oscillator generating drive signals,
• an assembly of latches receiving an input signal of the circuit, the latches being driven by the drive signals and generating samples by sampling of the input signal,
• a logic decoding circuit receiving samples generated by latches and accordingly driving the programmable ring oscillator,
• wherein the logic decoding circuit includes means for comparing samples two by two to determine whether a state transition has occurred in a time interval separating the two samples, this comparison being performed over at least two cycles, consecutive or not, of the ring oscillator, so that:
• if, during the second cycle, a comparable state transition is detected in the same interval, the control of the programmable ring oscillator is not modified,
• if, during the second cycle, a comparable state transition is detected in a subsequent interval, a decrease of the programmable ring oscillator period is ordered,
• if, during the second cycle, a comparable state transition is detected in a prior interval, an increase of the programmable ring oscillator period is ordered.