Self-compensating phase detector
AssigneeIntel Corporation
InventorLuke A. Johnson
Life of this patent
Estimating the term…
Abstract
A self compensating phase detector. Using two identical phase detectors introducing one of the phase detectors and a controlled variable phase shifter in a negative feedback loop shifts one dock signal enough such that the shifted signal compensates for existing static phase error. This self-compensation improves the accuracy of the phase difference measurement by significantly reducing the effect of static phase error. Moreover, this reduction remains true in spite of variations in process, temperature and voltage. Thus, inherent immunity of the invention to environmental conditions results in fewer failing parts during fabrication. Additionally, because the design is self-adjusting to environmental changes, design ease is significantly improved.
Claims15
An apparatus comprising:
- a first phase detector;
- a second phase detector that is a replica of the first phase detector;
- a phase shifter coupled in a feedback loop of the second phase detector, wherein the phase shifter output is coupled to an input of each of the first and second phase detectors, wherein the second phase detector receives a clock signal and a phase shift of the clock signal, shifted by the phase shifter, an amount of phase shift determined by a comparison between the clock signal and the phase shift of the clock signal;
- and
- an amplifier coupled between the output of the second phase detector and the phase shifter.
A method comprising the steps of:
- comparing, in a first phase detector, a first clock signal and a phase shifted first clock signal;
- adjusting phase shift of the first clock signal based on a result of a comparison of the first clock signal and the phase shifted first clock signal;
- and
- comparing in a second phase detector that is a replica of the first phase detector, the phase shifted first clock signal with a second clock signal.
A system comprising:
- a serial bus for transferring data responsive to a first clock signal;
- and
- a transceiver coupled to the serial bus, the transceiver responsive to a second clock signal, the transceiver including a first phase detector, a second phase detector and a phase shifter, the first phase detector and the phase shifter coupled in a negative feedback loop to shift one of the first clock signal and the second clock signal to compensate for a static phase error based on a comparison between the shifted signal and the signal before shifting wherein an amount of the shift by the phase shifter is determined from the comparison.
Dependencies are inferred from the claim text.