US 6,208,178 B1Granted

CMOS over voltage-tolerant output buffer without transmission gate

AssigneePericom Semiconductor Corp.

InventorBaohua Chen

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Abstract

An isolating output buffer is operated by a low-voltage Vcc power supply, yet can be put in a high-impedance state. The output buffer does not draw significant current when its output is driven by an external driver to a voltage above Vcc. The over-voltage on the output pad is coupled to the n-well under p-channel transistors through a fixed-gate p-channel transistor. The over-voltage from the n-well is then coupled to a source node through another p-channel transistor. The source node is the source of a p-channel transistor that drives the gate of a p-channel driver transistor driving the output pad. The source node is normally driven to Vcc by another p-channel transistor. The p-channel transistor can be split into two driver transistors that are separately driven by two isolating inverters or gates. The isolating gates have p-channel transistors connected to the source node. Using split drivers can reduce noise and di/dt when the two driver transistor are enabled at slightly different times. The output buffer is implemented entirely in CMOS without using bipolar transistors. The isolating output buffer is faster because it does not use a transmission gate in the speed path.

Claims20

Dependent claims

An over-voltage tolerant output buffer comprising:

an output pad for connecting to an external bus, the external bus being driven to an over-voltage above a power-supply voltage for the output buffer;
a p-channel driver transistor, coupled to the output pad, for driving the output pad to a higher voltage, the p-channel driver transistor being controlled by a gate node;
an n-well node, coupled to the p-channel driver transistor, for providing a substrate bias to the p-channel driver transistor;
a fixed-gate transistor, coupled between the output pad and the n-well node, for coupling the n-well node to the output pad when the over-voltage appears on the output pad;
an isolating gate for driving the gate node of the p-channel driver transistor, the isolating gate including an n-channel transistor for pulling the gate node to ground when the p-channel driver transistor is to be enabled, the isolating gate also including a p-channel transistor for coupling the gate node to a source node when the p-channel driver transistor is not enabled;
a well-source transistor, coupled between the n-well node and the source node, for coupling the over-voltage from the n-well node to the source node when the over-voltage appears on the output pad;
and
a supply transistor, coupled between the power-supply voltage and the source node, for applying the power-supply voltage to the source node when the over-voltage does not appear on the output pad,
whereby the over-voltage on the output pad is applied to the gate node of the p-channel driver transistor through the fixed-gate transistor, the n-well node, the well-source transistor, and the p-channel transistor in the isolating gate.

6 more elements

An output buffer for driving a bus comprising:

an input;
a circuit output;
an n-well substrate node;
a middle node;
a p-channel driver transistor, having a gate controlled by a driver-gate node, a drain coupled to the circuit output, and a source coupled to a power supply;
a logic gate, having the circuit output as an input, for generating a first signal;
a high-voltage inverter, receiving the first signal, for generating a second signal;
a first p-channel transistor, having a gate coupled to the power supply, a drain coupled to the n-well substrate node, and a source coupled to the circuit output;
a second p-channel transistor, having a gate coupled to the second signal, a source coupled to the power supply, and a drain coupled to the n-well substrate node;
a third p-channel transistor, having a gate controlled by the circuit output, a drain coupled to the middle node, and a source coupled to the power supply;
a fourth p-channel transistor, having a gate controlled by the first signal, a drain coupled to the middle node, and a source coupled to the -well substrate node;
a source-isolated inverter including:
an n-channel transistor with a gate coupled to the input, a drain coupled to the driver-gate node, and a source coupled to ground;
and
a p-channel transistor with a gate coupled to the input, a drain coupled to the driver-gate node, and a source coupled to the middle node,
whereby the source-isolated inverter drives the p-channel driver transistor from the middle node which is driven through the four p-channel transistor, the n-well substrate node, and the first p-channel transistor from the circuit output when the first signal is low.

13 more elements

An output buffer with a high-impedance state comprising:

well-bias means, coupled to an output, for connecting a well to the output when the output is in a high state and the output buffer is in the high-impedance state, and for otherwise connecting the well to a power supply;
pullup driver means for driving the output to a high state when the output buffer is not in the high-impedance state and a gate node is in a low state;
source-bias means for connecting the well to a middle-source node when the output is in a high state and the output buffer is in the high-impedance state, and for otherwise connecting the middle-source node to a power supply;
and
isolated inverter means, receiving an input indicating a state to drive the output to, for driving the gate node from the middle-source node when the output is to be driven to a low state or the output buffer is in the high-impedance state, and for driving the gate node to ground when the output is to be driven to a high state and the output buffer is not in the high-impedance state,
whereby an over-voltage on the output is coupled through the well-bias means to the well, and through the source-bias means to the middle-source node, and through the isolated inverter means to the gate node of the pullup driver means when the output buffer is in the high-impedance state.

3 more elements

Dependencies are inferred from the claim text.