System margin and core temperature monitoring of an integrated circuit

A circuit for monitoring performance of an integrated circuit comprising:

• a phase delay detection circuit coupled to an output pin of the integrated circuit and to a clock signal, the clock signal being used to clock circuitry within the integrated circuit, the circuitry within the integrated circuit generating an output signal on the output pin of the integrated circuit, wherein the phase delay detection circuit includes:
• digital signal generating means, coupled to the output pin of the integrated circuit, for generating a digital signal, wherein changes in phase delay between the output signal on the output pin of the integrated circuit and the clock signal result in changes in a duty cycle of the digital signal generated by the digital signal generating means, wherein the digital signal generating means comprises:
• a delay flip-flop having a D input, a clock input, a Q output and an inverted Q output, the clock signal being coupled to the clock input and the output signal being inverted and coupled to the D input,
• a first NAND gate having three inputs and an output, a first input being coupled to the inverted Q output, the second input being coupled to the inverted output signal and the third input being coupled to the clock signal,
• a second NAND gate having three inputs and an output, a first input being coupled to the Q output, the second input being coupled to the inverted output signal and the third input being coupled to the clock signal,
• a first gate having a signal input, a control input and an output, a VCC voltage being coupled to the signal input of the first gate, and the output signal of the first NAND gate being coupled to the control input, and
• a second gate having a signal input, a control input and an output, a reference voltage being coupled to the signal input of the second gate, and the output signal of the second NAND gate being coupled to the control input of the second gate;
• and
• integrating means for integrating the digital signal to produce an integrated signal, the integrated means having an input coupled to the output of the first gate and to the output of the second gate, wherein a voltage level of the integrated signal indicates relative phase delay between the output signal on the output pin of the integrated circuit and the clock signal.

A system comprising:

• an integrated circuit, the integrated circuit using a clock signal to generate an output signal on an output pin of the integrated circuit;
• and,
• a monitoring circuit which monitors core temperature of the integrated circuit, the monitoring circuit comprising
• a phase delay detection circuit coupled to the output pin of the integrated circuit and to the clock signal, the phase delay detection circuit including
• digital signal generating means, coupled to the output pin of the integrated circuit, for generating a digital signal, wherein changes in phase delay between the output signal on the output pin of the integrated circuit and the clock signal result in changes in a duty cycle of the digital signal generated by the digital signal generating means, and
• integrating means, coupled to the digital signal generating means, for integrating the digital signal to produce an integrated signal, a voltage level of the integrated signal indicating relative phase delay between the output signal on the output pin of the integrated circuit and the clock signal, and
• control means, coupled to the integrating means, for changing an operating frequency of the integrated circuit when the voltage level of the integrated signal indicates that the phase delay between the output signal and the clock signal is longer than a predetermined value.

A method for monitoring performance of an integrated circuit comprising the following steps:

• (a) externally monitoring core temperature of the integrated circuit, comprising the following substeps
• (a.1) placing the integrated circuit in a known state;
• and,
• (a.2) detecting changes in phase delay between an output signal on an output pin of the integrated circuit and a clock signal to determine the core temperature of the integrated circuit, wherein the clock signal is used to clock circuitry, within the integrated circuit, which generates the output signal;
• and
• (b) lowering an operating frequency of the integrated circuit when the changes detected in substep (a.2) indicate that the phase delay between the output signal and the clock signal is longer than a predetermined value.

A method comprising the following step:

• (a) monitoring core temperature of an integrated circuit, including the following substeps,
• (a.1) comparing phase delay between an output signal on an output pin of the integrated circuit and a clock signal used by the integrated circuit in generating the output signal,
• (a.2) generating a digital signal in response to the comparison made in substep (a.1), a duty cycle of the digital signal indicating phase delay between the output signal and the clock signal, and
• (a.3) integrating the digital signal to produce an integrated signal, the integrated signal having a voltage level which indicates core temperature of the integrated circuit;
• and,
• (b) lowering an operating frequency of the integrated circuit when the voltage level of the integrated signal indicates that the phase delay between the output signal and the clock signal is longer than a predetermined value.