Internal clock jitter detector

A circuit comprising:

• a delay circuit coupled to receive a clock signal to generate a delayed clock signal;
• and
• a phase comparing element coupled to receive the clock signal and the delayed clock signal, the phase comparing element to measure a phase difference between the clock signal and the delayed clock signal.

A circuit comprising:

• a clock signal generator;
• and
• a phase comparing element coupled to the clock signal generator to receive a first clock signal and a second clock signal derived from the first clock signal, the phase comparing element to measure a phase difference between the first clock signal and the second clock signal.

A method for detecting error in a clock signal, the method comprising the steps of:

• delaying a clock signal by an average duration to provide a delayed clock signal;
• and
• comparing the delayed clock signal with an instantaneous clock signal, wherein the delayed clock signal is derived from the instantaneous clock signal.

A method comprising the steps of:

• generating a reference clock signal;
• and
• comparing the reference clock signal with an instantaneous clock signal, wherein the reference clock signal is derived from the instantaneous clock signal.