Technique for preconditioning I/Os during reconfiguration
AssigneeAltera Corporation
InventorVincent T. Bocchino
Life of this patent
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Abstract
A technique for configuring programmable integrated circuits. The technique involves preconditioning or predefining the outputs and I/Os of a programmable integrated circuit before the device is programmed or reconfigured. When the device is programmed, the outputs and I/Os of the programmable integrated circuit will be driven to the preconditioned or predefined states. The technique may be implemented in conformance with the IEEE 1149.1 boundary scan architecture standard. Standard IEEE 1149.1 instructions may be used. The technique may also be used during in-system programming of programmable integrated circuits.
Claims27
A method of configuring a programmable integrated circuit comprising:
- providing a user-selected input to the programmable integrated circuit;
- storing the user-selected input in a register, wherein the register is a JTAG boundary scan register of the programmable logic integrated circuit;
- driving a pad to a state based on the user-selected input when the programmable integrated circuit is being reconfigured;
- and
- configuring the programmable integrated circuit.
A method of programming a programmable logic device comprising:
- preconditioning outputs of the programmable logic device using a JTAG boundary scan cell before entering a reconfiguration mode, wherein output pads of the programmable logic device are placed in preconditioned states during the reconfiguration mode;
- and
- configuring programmable elements of the programmable logic device during the reconfiguration mode.
A method of configuring a programmable integrated circuit comprising:
- inputting a first user-selected bit and a second user-selected bit into a register of the programmable integrated circuit;
- when the programmable integrated circuit is being configured, transferring the first user-selected bit to a data input of a tristate buffer and the second user-selected bit to an enable input of the tristate buffer;
- and
- configuring the programmable integrated circuit.
A method of configuring a programmable integrated circuit comprising;
- serially loading a first register with user-input bits;
- transferring in parallel the user-input bits from the first register to a second register;
- and
- when the programmable integrated circuit is being configured, controlling the tristate buffer using the user-input bits in a second register.
A method of reconfiguring a programmable circuit comprising:
- providing a user-selected input;
- driving a pad with a tristate buffer controlled by the user-selected input when the programmable circuit is being configured, wherein the user-selected input is coupled to a first input of a multiplexer and data signal is coupled to a second input of the multiplexer, wherein an output of the multiplexer is coupled to the tristate buffer, and a control node of the multiplexer is controlled by a signal indicating whether the programmable circuit is being configured;
- and
- configuring the programmable circuit.
A programmable integrated circuit comprising:
- a first multiplexer coupled to internal logical data;
- a boundary scan register, coupled to the first multiplexer, wherein in a first mode the first multiplexer permits parallel loading of internal logical data into the boundary scan register, and in a second mode, the first multiplexer permits serial loading of the boundary scan register;
- an update register coupled to the boundary scan register;
- an output buffer to place a pad into a logic high state, a logic low state, or a high impedance state;
- and
- a second multiplexer, selectively coupling the update register or the internal logical data to the output buffer, wherein a control input to the second multiplexer is coupled to a reconfiguration signal indicating whether the integrated circuit is in a reconfiguration mode, and when in the reconfiguration mode, the update register is coupled to the output buffer.
The programmable integrated circuit of claim 26 wherein contents of the boundary scan register are transferred in parallel to the update register in response to the an update signal.
Dependencies are inferred from the claim text.