An integrated circuit comprising a substrate, an interconnect formed on the substrate, and a passivation layer formed on the interconnect and the substrate, wherein the interconnect has substantially vertical sidewalls extending between top portions of the interconnect and bottom portions of the interconnect, and a rounded corner portion extending along the bottom portions of the interconnect, thereby reducing stress in the passivation layer, wherein the rounded corner portion is a spacer positioned along the bottom portions of the interconnect, and wherein the spacer is formed of a flowable insulating material.