US 6,207,992 B1 · Vertical floating gate transistor with epitaxial channel

Abstract

A vertical floating gate transistor includes an epitaxially formed channel between its lower source/drain region and upper source/drain region, with a floating gate electrode in a trench that extends vertically through those regions and a control or programming gate electrode above and separated from the floating gate electrode. A process for forming the vertical floating gate transistor implants the substrate to provide the lower source/drain region, then forms an epitaxial layer that provides the channel over the previously formed lower source/drain region. Then, the upper source/drain region is implanted above the lower source/drain region and epitaxial channel layer, followed by formation of a vertical trench and the floating and control gates. Forming the epitaxial layer over a previously implanted lower source/drain region allows independent control of the resistivity of the lower source/drain region, such that it can have low resistivity, facilitating device symmetry. Also, the epitaxial channel layer has improved doping uniformity over diffusion type channel region, lowering channel length and increasing performance and yield. Finally, the source/drain regions may incorporate two separate dopants to provide an extended region that further minimizes the channel length while providing higher punch through voltage levels and retaining low resistivity.

Claims9

Dependent claims

A vertical floating gate transistor arranged on a substrate of a first conductivity type, the vertical floating gate transistor being fabricated according to the following steps:

doping a first area of the substrate to form a first doped region having a second conductivity type, said doping in the first area including implanting the substrate with a first dopant and a second dopant that differs from the first dopant, the first and second dopants forming the first doped region, wherein the first dopant has a higher diffusion rate than the second dopant;
after the step of doping in a first area, forming an epitaxial layer of the first conductivity type over the first doped region, a portion of the epitaxial layer providing a channel for the vertical floating gate transistor, wherein the step of forming the epitaxial layer causes the first and second dopants to diffuse, the first dopant extending further into the portion of the epitaxial layer that provides the channel than the second dopant;
doping in a second area to form a second doped region, the second doped region having the second conductivity type and residing above the portion of the epitaxial layer that provides the channel;
forming a trench that extends through at least a portion of the first doped region, the epitaxial layer, and the second doped region;
forming a first gate electrode in the trench, the first gate electrode being separated from the first and second doped regions by a first insulating layer;
and
forming a second gate electrode that is separated from the first gate electrode by a second insulating layer.

4 more elements

Dependencies are inferred from the claim text.

Vertical floating gate transistor with epitaxial channel

Life of this patent

Vertical floating gate transistor with epitaxial channel

Life of this patent

Abstract

Claims9