DRAM memory cell and array having pass transistors with surrounding gate

A dynamic random access memory cell, comprising:

• a storage capacitor;
• and
• a pass transistor formed on an insulating layer, the pass transistor including
• a source region having a source width along a width direction,
• a drain region having a drain width along the width direction,
• a channel region extending between the source region and the drain region, generally perpendicular to the width direction, the channel region having a channel width along the width direction that is less than the drain width, the channel region being defined in the width direction by a bottom surface disposed on the insulating surface and a control surface that extends upward from the bottom surface,
• a first gate insulating layer formed on the control surface of the channel region, and
• a first surrounding gate formed over at least a portion of the control surface, and being separated therefrom by the first gate insulating layer.

A dynamic random access memory array, comprising:

• a plurality of memory cells, arranged into a plurality of generally parallel rows, each memory cell including
• a pass transistor having
• a source region formed within a silicon mesa disposed on a substrate insulating layer,
• a drain region formed within the silicon mesa,
• a channel region formed within the silicon mesa between the source region and the drain region, the channel region including a control surface having at least a first side surface that extends generally upward from the substrate insulating layer,
• a control gate formed over the control surface of the channel region, and separated therefrom by a gate insulating layer, and
• a storage capacitor coupled to the drain region, the storage capacitor including
• a storage node coupled to, and extending over the drain region,
• a capacitor dielectric formed over the storage node, and
• a common plate formed over the storage nodes of a plurality of memory cells;
• and
• a word line associated with each row, each word line being coupled to the first gates of the memory cells within its respective row.