Self-aligned contact formation for semiconductor devices

A method of making an integrated circuit comprising:

• forming one or more gate stacks;
• forming an insulating film at least partially covering one or more of the gate stacks, wherein the insulating film comprises a tetraethyloxysilicate (TEOS) layer and a borophosphosilicate glass (BPSG) layer;
• planarizing the insulating film;
• and
• forming one or more gate contact openings through the planarized insulating film.

A method of making an integrated circuit, comprising:

• forming one or more gate stacks, wherein each gate stack comprises:
• gate dielectric on a base layer;
• a conductor on the gate dielectric;
• and
• an insulator on the conductor;
• forming an insulating film at least partially covering one or more of the gate stacks, wherein the insulating film comprises a tetraethyloxysilicate (TEOS) layer and a borophosphosilicate glass (BPSG) layer;
• planarizing the insulating film;
• and
• forming a gate contact opening through at least a portion of the planarized insulating film.

A method of forming a dynamic random access memory (DRAM), comprising:

• forming one or more gate stacks, with each gate stack having one or more sidewalls;
• forming one or more spacers on each of the one or more sidewalls;
• forming an insulating film over at least a portion of the gate stacks and spacers;
• planarizing the insulating film;
• and
• forming one or more gate contact openings after forming the gate stacks.

A method of forming contacts in a dynamic random access memory (DRAM), comprising:

• forming one or more gate stacks on a surface, with each gate stack having one or more substantially vertical sidewalls;
• forming one or more spacers on the vertical sidewalls of one or more of the gate stacks;
• forming an insulative layer over the one or more gate stacks;
• forming one or more gate and bitline contact openings through the insulative layer;
• and
• forming gate and bitline contacts in the one or more gate and bitline contact openings.

A method of forming an integrated memory circuit, comprising:

• forming one or more groups of n and p wells on a base layer;
• forming a gate dielectric on the base layer;
• forming a conductor on the gate dielectric;
• forming silicon nitride on the conductor;
• forming gate stacks from the gate dielectric, the conductor, and the silicon nitride, with each gate stack having one or more sidewalls;
• forming nitride spacers on the sidewalls of the gate stacks;
• forming borophosphosilicate glass (BPSG) and tetraethyloxysilicate (TEOS) over at least portions of the nitride spacers and one or more of the gate stacks;
• planarizing the BPSG with chemical mechanical planarization to form a substantially flat topography on the surface of the DRAM;
• forming gate and bitline contact openings through the planarized BPSG;
• forming gate and bitline contacts in self-alignment to the gate stacks.

A method of making an integrated memory circuit, comprising:

• forming one or more gate stacks, with each gate stack having one or more sidewalls;
• forming nitride spacers on the sidewalls of the gate stacks;
• and
• forming an insulative structure comprising a layer of borophosphosilicate glass (BPSG) and a layer of tetraethyloxysilicate (TEOS) over at least portions of the nitride spacers and one or more of the gate stacks.

A method of making an integrated memory circuit, comprising:

• forming one or more gate stacks, with each gate stack having one or more sidewalls and one or more conductive portions;
• forming nitride spacers on the sidewalls of the gate stacks;
• forming an insulative structure over the gate stacks;
• planarizing the insulative structure;
• and forming one or more bitline contacts, with each contact extending through the planarized insulative and electrically coupled to the conductive portion of at least one of the gate stacks.

A method of making an integrated memory circuit, comprising:

• forming one or more gate stacks, with each gate stack having one or more sidewalls and one or more conductive portions;
• forming nitride spacers on the sidewalls of the gate stacks;
• forming an insulative structure over the gate stacks;
• planarizing the insulative structure;
• and
• forming one or more gate contacts, with each contact extending through the planarized insulative structure and electrically coupled to the conductive portion of at least one of the gate stacks.

An integrated-circuit structure comprising:

• one or more gate stacks, with each gate stack having one or more sidewalls and one or more conductive portions;
• one or more nitride spacers on the sidewalls of the gate stacks;
• a substantially planar insulative structure overlying one or more of the gate stacks;
• and
• one or more gate contacts, with each contact extending through the substantially planar insulative structure and electrically coupled to the conductive portion of at least one of the gate stacks.

An integrated-circuit structure comprising:

• one or more gate stacks, with each gate stack having one or more sidewalls and one or more conductive portions;
• one or more nitride spacers on the sidewalls of the gate stacks;
• a substantially planar insulative structure overlying one or more of the gate stacks and comprising a layer of borophosphosilicate glass (BPSG) and a layer of tetraethyloxysilicate (TEOS);
• and
• one or more gate contacts, with each contact extending through the substantially planar insulative structure and electrically coupled to the conductive portion of at least one of the gate stacks.