US 6,207,564 B1 · Method of forming self-aligned isolated plugged contacts

Abstract

A method for preparing an SRAM or DRAM structure on a substrate with an oppositely doped well therein, a field oxide region extending above and between the well and the substrate, first and second N-MOS transistors on the silicon substrate, and a P-MOS transistor on the silicon well. The source and drain regions of each of the P-MOS transistor and the first and second N-MOS transistors each have a polysilicon plug making contact therewith. Each polysilicon plug is isolated one from another by nitride spacers, has the same doping as the region with which it makes contact, and is self-aligned to the nitride spacers lining the passage of the polysilicon plugs to their respective contacts on either the silicon substrate or the silicon well. The self-aligned nature of the polysilicon plugs is due to the nitride spacers formed by etchant selectivities and photoresist masks.

Claims34

Dependent claims

A method of forming contacts comprising:

forming a first mask upon a semiconductor substrate;
patterning the first mask with a first pattern opening therein to expose a first contact on the semiconductor substrate, the first contact having a first shape;
forming a first electrically conductive material upon the first contact;
forming a second mask upon the semiconductor substrate;
patterning the second mask with a second pattern opening therein to expose a second contact on the semiconductor substrate, wherein the second pattern opening overlaps the first pattern opening and the second contact has a second shape that is aligned with the first shape at an interface therebetween;
forming a dielectric upon the semiconductor substrate;
and
forming a second electrically conductive material upon the second contact, the first and second electrically conductive materials having said dielectric situated therebetween.

5 more elements

A method for preparing an integrated circuit structure, said integrated circuit structure including a doped silicon substrate, and five MOS devices, each said MOS device being sealed under a separate layer of nitride in contact with the silicon substrate, there being a first bitline contact and a second bitline contact, each said bitline contact being in contact with the silicon substrate, the first bitline contact being situated between the separate nitride layers of the first and second MOS devices, and the second bitline contact being between the separate nitride layers of the fourth and fifth MOS devices, there being a first cellnode contact and a second cellnode contact, each said cellnode contact being in contact with the silicon substrate, the first cellnode contact being between the separate nitride layers of the third and fourth MOS devices, the second cellnode contact being between the separate nitride layers of the third and fourth MOS devices, the method comprises the steps of:

applying a passivation layer of oxide over and between first through the fifth MOS devices;
applying a first layer of photoresist over the passivation layer of oxide;
exposing the portions of the first layer of photoresist that are situated immediately above and aligned with:
both the first cellnode contact and at least a portion of the third MOS device;
and
both the first cellnode contact and at least a portion of the fourth MOS device;
developing the first layer of photoresist;
etching with a first etch chemistry selective to nitride, silicon, and polysilicon through the passivation layer of oxide to expose a first etch contact series comprising the first and second cellnode contacts;
depositing a first layer of thin nitride film over the passivation oxide layer, and the first etch contact series;
etching anisotropically with a second etch chemistry the first layer of thin nitride film so as to form a first nitride spacer above and in contact with the nitride layer of the first MOS device, a second nitride spacer above and in contact with the nitride layer of the second MOS device, a third and fourth nitride spacer above and in contact with the nitride layer of the third MOS device, a fifth nitride spacer above and in contact with the nitride layer of the fourth MOS device, and a sixth nitride spacer above and in contact with the nitride layer of the fifth MOS device, each of the first through sixth nitride spacers being vertically oriented and bounded on one side thereof to the passivation layer of oxide and, and each of the second through fifth nitride spacers being bounded on an opposite side thereof by an opening to one of said first and second cellnode contacts;
applying a first conductive layer over the passivation oxide layer, and the first etch contact series;
applying a second layer of photoresist over the integrated circuit structure;
exposing the second layer of photoresist that are situated immediately above and substantially aligned with:
the portion thereof from the first nitride spacer to the second nitride spacer;
and
the portion from the fifth nitride spacer to the sixth nitride spacer;
developing the second layer of photoresist;
etching with a third etch chemistry through the layer of thin oxide film over the first conductive layer;
etching with a fourth etch chemistry through the first conductive layer with selectivity to oxide and to nitride;
etching with a fifth etch chemistry selective to nitride, polysilicon, and silicon through the passivation layer of oxide to expose the first and second bitline contacts;
depositing a second layer of thin nitride film over the area extending from the first MOS device to the fifth MOS device;
etching anisotropically with a sixth etch chemistry the second layer of thin nitride film so as to form a seventh nitride spacer having a length greater than the first nitride spacer and being above and in contact with the nitride layer of the first MOS device, to form a longer linear extension of the second nitride spacer, and an eighth nitride spacer having a length greater than the fifth nitride spacer and above and in contact with the nitride layer of the fourth MOS device, and to form a longer linear extension of the sixth nitride spacer above and in contact with the nitride layer of the fifth MOS device, the seventh nitride spacer being bounded on one side thereof to both the passivation layer of oxide and the first conductive layer, and on an opposite thereof to an opening to the first bitline contact, the longer extension of second nitride spacer being bounded on one side thereof to the first conductive layer and on an opposite side thereof to an opening to the first bitline contact, the eight nitride spacer being bounded on one side thereof to both the passivation layer of oxide and the first conductive layer, and on an opposite side thereof to an opening to the second bitline contact, and the longer extension of sixth nitride spacer being bounded on one side thereof to the first conductive layer, and on an opposite side thereof to an opening to the second bitline contact, each of said seventh nitride spacer, extension of the second nitride spacer, eight nitride spacer, and extension of the sixth nitride spacer being substantially vertically oriented;
depositing a second conductive layer over the area between the first MOS device and the fifth MOS device so as cover the first and second bitline contacts;
and
performing a chemical-mechanical polishing step, whereby the first conductive layer forms two separated contacts, respectively, with the first and second cellnode contacts, and the second conductive layer forms two separated contacts, respectively, to the first and second bitline contacts.

22 more elements

Dependencies are inferred from the claim text.

Method of forming self-aligned isolated plugged contacts

Life of this patent

Method of forming self-aligned isolated plugged contacts

Life of this patent

Abstract

Claims34