Gap filling process in integrated circuits using low dielectric constant materials

A method for fabricating multilevel metal interconnections having low dielectric constant insulators on a substrate comprising the steps of:

• providing a semiconductor substrate having semiconductor devices in and on said substrate;
• depositing a first insulating layer over said devices, and further having contact openings in said first insulating layer for electrical contacts to said devices;
• forming a metal barrier layer on said insulating layer and in said contact openings;
• depositing a first conductive layer for contacting said contact openings and forming a metal stack on the interlevel dielectric layer (ILD);
• depositing hard mask layer of silicon nitride and then silicon oxide on top of metal layer, with silicon oxynitride DARC, dielectric anti-reflective coating on top of metal stack;
• patterning said metal stack consisting of hard mask layer and metal stack layer with said metal barrier layer to form first metal lines as interconnections for said devices;
• coating a layer of low dielectric constant insulating material on and in between said patterned interconnect metal lines;
• curing the low dielectric constant material;
• chemical mechanical polishing (CMP) back and planarizing the surface of said low dielectric constant material with hard mask on top of metal stack;
• stopping the CMP polishing on the hard mask layer;
• coating the surface with a second layer of low dielectric material;
• curing the low dielectric constant material;
• depositing a second hard mask layer of silicon nitride and then silicon oxide over the second low dielectric constant layer;
• defining via openings and etching for vias to open vias to the underlying interconnect metal;
• depositing conductive metal and forming metal contacts by chemical mechanical polishings (CMP) the excess metal, stopping on the polishing on the hard mask layer, thus forming low dielectric constant, low capacitance structures.

A method for fabricating multilevel metal interconnections having low dielectric constant insulators on a substrate comprising the steps of:

• providing a semiconductor substrate having semiconductor devices in and on said substrate;
• depositing a first insulating layer over said devices, and further having contact openings in said first insulating layer for electrical contacts to said devices;
• forming a metal barrier layer on said insulating layer and in said contact openings;
• depositing a first conductive layer for contacting said contact openings and forming a metal stack with a silicon oxynitride DARC, dielectric anti-reflective coating, on top of metal, on the interlevel dielectric layer (ILD);
• depositing hard mask layer of silicon nitride and then silicon oxide on top of metal layer;
• patterning said metal stack consisting of hard mask layer and metal stack layer with said metal barrier layer to form first metal lines as interconnections for said devices;
• coating a layer of low dielectric constant insulating material on and in between said patterned interconnect metal lines;
• curing the low dielectric constant material;
• chemical mechanical polishing (CMP) back and planarizing the surface of said low dielectric constant material with hard mask on top of metal stack;
• stopping the CMP polishing on the hard mask layer;
• depositing a layer of adhesion promoter over the hard mask and low dielectric constant layer;
• depositing a silicon oxide cap layer on the adhesion promoter layer
• defining via openings and etching to open electrical contacts to the underlying interconnect metal;
• depositing conductive metal over the via openings;
• removing the excess said conductive metal by CMP;
• patterning of said conductive layer to form the next level of metal interconnections.