Forming and filling a recess in interconnect for encapsulation to minimize electromigration
AssigneeAdvanced Micro Devices, Inc.
InventorsPin-Chin C. Wang, Lu You
Life of this patent
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AssigneeAdvanced Micro Devices, Inc.
InventorsPin-Chin C. Wang, Lu You
Estimating the term…
A strong interface is fabricated by forming and filling a recess on top of an interconnect between the interconnect and an encapsulating layer to prevent the lateral drift of material from the interconnect along the bottom of the encapsulating layer. A recess is formed within the top surface of the interconnect, and diffusion barrier material is deposited within the recess on the top surface of the interconnect. The diffusion barrier material may be epitaxially grown from the interconnect during the deposition of the diffusion barrier material within the recess to promote adhesion of the diffusion barrier material to the interconnect. An encapsulating layer is deposited on top of the diffusion barrier material. The diffusion barrier material and the encapsulating layer are comprised of a similar chemical element to promote adhesion of the diffusion barrier material to the encapsulating layer. The diffusion barrier material within the recess of the interconnect prevents lateral drift of material comprising the interconnect along the encapsulating layer. When the layer of encapsulating dielectric is comprised of silicon nitride, a nitrided surface may be formed on top of the diffusion barrier material by exposing the top of the diffusion barrier material to nitrogen plasma before depositing the encapsulating layer of silicon nitride on top of the diffusion barrier material. The present invention may be used to particular advantage when the interconnect is a copper interconnect and when the layer of encapsulating layer is comprised of silicon nitride.
A method for encapsulating a top surface of an interconnect of an integrated circuit, said interconnect being within an insulating layer, the method including the steps of:
A method for encapsulating a top surface of copper interconnect of an integrated circuit, said copper interconnect being within an insulating layer of silicon dioxide, the method including the steps of:
Dependencies are inferred from the claim text.