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US 6,207,543 B1Granted
Metallization technique for gate electrodes and local interconnects
AssigneeVLSI Technology, Inc.
InventorsIan Robert Harvey, Xi-Wei Lin
Life of this patent
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Abstract
A process for making an integrated circuit is disclosed. This technique includes electrically interconnecting a pair of adjacent transistors positioned along a semiconductor substrate by coating with an oxide layer, planarizing the layer, then forming a trench exposing a contact region for each transistor. This trench is filled with a metal, such as tungsten to provide an electrical interconnection of the contact regions. The metal is then planarized to be approximately coplanar with the planarized oxide layer. Metal gate electrodes are formed at the same time as the interconnection. Additional processing includes depositing an IMO layer over the planarized metal and oxide and defining additional interconnections through the IMO layer.
Claims18
A process for manufacturing an integrated circuit, comprising the steps of:
- (a) defining a region of a silicon substrate for formation of a first field effect transistor with a first source and a first polysilicon gate adjacent a second field effect transistor with a second source and a second polysilicon gate, the first and second transistors sharing a common drain, the first and second polysilicon gates being spaced apart from one another to define a gap therebetween;
- (b) depositing a silicon dioxide layer on the region, the silicon dioxide layer covering the region and filling the gap defined between the first and second polysilicon gates;
- (c) removing a portion of the silicon dioxide layer by chemical mechanical polishing to expose a portion of the polysilicon gate for each of the pair of transistors to define a first surface;
- (d) etching the first and second polysilicon gates to define a first recess in the first polysilicon gate and a second recess in the second polysilicon gate;
- (e) establishing a photoresist pattern on the region, the photoresist pattern defining an opening over the common drain and at least a portion of the first recess;
- (f) selectively etching a portion of the silicon dioxide layer corresponding to the opening to define a third recess exposing at least a portion of the common drain;
- (g) removing the photoresist pattern;
- (h) covering the region with a metallic layer, the metallic layer filling the first, second, and third recesses;
- (i) planarizing the region by removing a portion of the metallic layer to define a second surface, the second surface including a first metallic region interconnecting the first gate and the common drain, a second metallic region provided by metal in the second recess, and an oxide region positioned between the first and second metallic regions;
- and
- (j) completing formation of the first and second field effect transistors.
8 more elements
A method of manufacture, comprising:
- (a) providing a number of transistor gates projecting from a semiconductor substrate, wherein at least a selected one of said gates includes a polysilicon portion in direct contact with an insulation gate pad, the insulation gate pad being in contact with the substrate;
- (b) coating the gates and substrate with a dielectric layer;
- (c) planarizing the layer to define a surface including an entire exposed polysilicon portion of each of the gates;
- (d) forming a recess receding from the surface by removing material from the layer and by removing a surface layer of the entire exposed polysilicon portion of the selected one of the gates, the recess exposing connection region along the substrate;
- and
- (e) depositing a conductive material into the recess to provide a local electrical interconnection between the polysilicon portion of the selected one of the gates and the connection region.
3 more elements
A method of manufacture, comprising:
- (a) providing a number of electronic device structures projecting from a semiconductor substrate;
- (b) establishing a first layer of dielectric material to fill space between the structures;
- (c) chemically-mechanically polishing the first layer to define a surface and expose a portion of one of the structures;
- (d) forming a recess in the portion exposed by said polishing and a trench through the first layer, the trench intersecting the recess and selectively exposing a connection region on the substrate;
- and
- (e) depositing a conductive material in the recess and trench to provide a local electrical interconnection between the portion and the connection region, wherein the local electrical interconnection and the first layer are substantially coplanar after said depositing.
3 more elements
A method of manufacture, comprising:
- (a) providing a number of transistor gates projecting from a semiconductor substrate;
- (b) coating the gates and substrate with a dielectric layer;
- (c) chemically-mechanically planarizing the layer to define a surface including an entire exposed polysilicon portion of each of the gates;
- (d) forming a recess receding from the surface by removing material from the layer and by removing a surface layer of the entire exposed polysilicon portion of a selected one of the gates, the recess exposing a connection region along the substrate;
- and
- (e) depositing a conductive material into the recess to provide a local electrical interconnection between the selected one of the gates and the connection region.
3 more elements
Dependencies are inferred from the claim text.